DATASHEET
ISL5216
Four-Channel Programmable Digital Downconverter
The ISL5216 Quad Programmable Digital Downconverter
(QPDC) is designed for high dynamic range applications
such as cellular basestations where multiple channel
processing is required in a small physical space. The QPDC
combines into a single package a set of four channels which
include: digital mixers, a quadrature carrier NCO, digital
filters, a resampling filter, a Cartesian-to-polar coordinate
converter and an AGC loop.
The ISL5216 accepts four channels of 16-bit fixed or up to
14-bit mantissa/3-bit exponent floating point real or complex
digitized IF samples which are mixed with local quadrature
sinusoids. Each channel carrier NCO frequency is set
independently by the microprocessor. The output of the
mixers are filtered with a CIC and FIR filters, with a variety of
decimation options. Gain adjustment is provided on the
filtered signal. The digital AGC provides a gain adjust range
of up to 96dB with programmable thresholds and slew rates.
A cartesian to polar coordinate converter provides
magnitude and phase outputs. A frequency discriminator is
also provided to allow FM demodulation. Selectable outputs
include I samples, Q samples, Magnitude, Phase,
Frequency and AGC gain. The output resolution is
selectable from 4-bit fixed point to 32-bit floating point.
Output bandwidths in excess of 1MHz are achievable using
a single channel. Wider bandwidths are available by
cascading or polyphasing multiple channels.
FN6013
Rev.3.00
July 13, 2007
Features
• Up to 95MSPS Input
• Four Independently Programmable Downconverter
Channels in a single package
• Four Parallel 17-Bit Inputs providing 16-bit fixed or one of
several 17-bit floating point formats
• 32-Bit Programmable Carrier NCO with > 115dB SFDR
• 110dB FIR Out of Band Attenuation
• Decimation from 4 to >65536
• 24-bit Internal Data Path
• Digital AGC with up to 96dB of Gain Range
• Filter Functions
- 1- to 5-Stage CIC Filter
- Halfband Decimation and Interpolation FIR Filtering
- Programmable FIR Filtering
- Resampling FIR Filtering
• Cascadable Filtering for Additional Bandwidth
• Four Independent Serial Outputs
• 2.5V Core, 3.3V I/O Operation
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Narrow-Band TDMA through IS-95 CDMA Digital Software
Radio and Basestation Receivers
• Wide-Band Applications: W-CDMA and UMTS Digital
Software Radio and Basestation Receivers
Ordering Information
PART NUMBER
ISL5216KI
ISL5216KI-1
ISL5216KIZ (Note)
ISL5216KI-1Z (Note)
PART MARKING
ISL5216KI
ISL5216KI-1
ISL5216KIZ
ISL5216KI-1Z
TEMP RANGE (°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
196 Ld 0.8mm BGA
196 Ld 1.0mm BGA
196 Ld 0.8mm BGA (Pb-free)
196 Ld 1.0mm BGA (Pb-free)
PKG. DWG. #
V196.12x12
V196.15x15
V196.12x12
V196.15x15
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6013 Rev.3.00
July 13, 2007
Page 1 of 65
ISL5216
Block Diagram
P
TEST
REGISTER
INPUT SELECT,
FORMAT,
DEMUX
LEVEL
DETECTOR
SCLK
A(15:-1)
ENIA
I
NCO/MIXER/CIC
Q
CHANNEL 0
FIR FILTERS,
AGC,
CARTESIAN-TO-POLAR
COORDINATE
CONVERTER
SYNCA
SD1A
SD2A
INPUT SELECT,
FORMAT,
DEMUX
B(15:-1)
ENIB
INPUT SELECT,
FORMAT,
DEMUX
I
NCO/MIXER/CIC
Q
CHANNEL 1
C(15:-1)
ENIC
INPUT SELECT,
FORMAT,
DEMUX
D(15:-1)
CHANNEL 2
ENID
I
NCO/MIXER/CIC
Q
BUS
ROUTING
FIR FILTERS,
AGC,
CARTESIAN-TO-POLAR
COORDINATE
CONVERTER
OUTPUT
SELECT,
FORMAT,
SERIALIZE
SYNCC
SD1C
SD2C
FIR FILTERS,
AGC,
CARTESIAN-TO-POLAR
COORDINATE
CONVERTER
SYNCB
SD1B
SD2B
INPUT SELECT,
FORMAT,
DEMUX
I
NCO/MIXER/CIC
Q
CHANNEL 3
FIR FILTERS,
AGC,
CARTESIAN-TO-POLAR
COORDINATE
CONVERTER
SYNCD
SD1D
SD2D
CLK
RESET
SYNCI
SYNCO
SYNCI0
SYNCI1
SYNCI2
SYNCI3
TRST
TCLK
TMS
TDI
TDO
INTRPT
P
INTERFACE
P(15:0)
ADD(2:0)
RD
or
RD/WR
WR
or
DSTRB
P
MODE
CE
FN6013 Rev.3.00
July 13, 2007
Page 2 of 65
ISL5216
Pinout
196 LD BGA
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
A5
B
A3
C
A1
D
B15
E
B13
F
B11
G
B9
H
CLK
J
B7
K
B5
L
B3
M
B1
N
C15
P
C13
C11
C9
C7
C5
C3
C1
ENIC
D14
D12
D10
D8
D6
D4
C14
C10
C8
GND
VCC1
GND
VCC1
GND
VCC2
D9
D7
D5
D2
B0
C12
C6
C4
C2
C0
D15
D13
D11
ENID
D3
D1
D0
B2
ENIB
TDI
Cm1
Dm1
CE
RD
WR
VCC1
B4
Bm1
P
MODE
P1
GND
P0
GND
B6
P3
VCC1
P2
VCC2
B8
TRST
SYNCI0
P5
GND
P4
GND
GND
TCLK
SYNCI1
P7
VCC1
P6
VCC1
B10
TMS
SYNCI2
P9
GND
P8
GND
B12
P11
VCC2
P10
A0
B14
Am1
TDO
SYNCI3
ADD2
RESET
P13
P12
A2
A4
ENIA
A12
A14
SD2A
SD1B
SD2B
SD2C
SD2D
INTRPT
P15
P14
A6
A8
A10
VCC1
GND
VCC1
GND
VCC2
GND
SD1C
SD1D
ADD0
ADD1
A7
A9
A11
A13
A15
SD1A
SYNCA SYNCB
SCLK
SYNCC SYNCD SYNCI SYNCO
POWER PIN
GROUND PIN
SIGNAL PIN
THERMAL BALL
NC (NO CONNECTION)
VCC1 = +2.5V CORE SUPPLY VOLTAGE
VCC2 = +3.3V I/O SUPPLY VOLTAGE
FN6013 Rev.3.00
July 13, 2007
Page 3 of 65
ISL5216
Pin Descriptions
NAME
POWER SUPPLY
VCC1
VCC2
GND
INPUTS
A(15:0), Am1
B(15:0), Bm1
C(15:0), Cm1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Dm1
ENIA
ENIB
ENIC
ENID
CONTROL
CLK
SYNCI
I
I
Input clock. All processing in the ISL5216 occurs on the rising edge of CLK.
Global synchronization input signal. Used to align the processing with an external event or with other ISL5216
or HSP50216 devices. SYNCI can update the carrier NCO, reset decimation counters, restart the filter
compute engine, and restart the output section among other functions. For most of the functional blocks, the
response to SYNCI is programmable and can be enabled or disabled. This signal is connected to all four
channels and is included for backward compatibility with HSP50216 designs.
Synchronization input signal for channel 0. Same functions as SYNCI but connects only to channel 0. This pin
is internally pulled low to allow it to be left unconnected.
Synchronization input signal for channel 1. Same functions as SYNCI but connects only to channel 1. This pin
is internally pulled low to allow it to be left unconnected.
Synchronization input signal for channel 2. Same functions as SYNCI but connects only to channel 2. This pin
is internally pulled low to allow it to be left unconnected.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Parallel Data Input bus A. Sampled on the rising edge of clock when ENIA is active (low). Am1 has internal
weak pull-down.
Parallel Data Input bus B. Sampled on the rising edge of clock when ENIB is active (low). Bm1 has internal
weak pull-down.
Parallel Data Input bus C. Sampled on the rising edge of clock when ENIC is active (low). Cm1 has internal
weak pull-down.
Parallel Data Input D15 or tuner channel 0 COF.
Parallel Data Input D14 or tuner channel 0 COFSync.
Parallel Data Input D13 or tuner channel 0 SOF.
Parallel Data Input D12 or tuner channel 0 SOFSync.
Parallel Data Input D11 or tuner channel 1 COF.
Parallel Data Input D10 or tuner channel 1 COFSync.
Parallel Data Input D9 or tuner channel 1 SOF.
Parallel Data Input D8 or tuner channel 1 SOFSync.
Parallel Data Input D7 or tuner channel 2 COF.
Parallel Data Input D6 or tuner channel 2 COFSync.
Parallel Data Input D5 or tuner channel 2 SOF.
Parallel Data Input D4 or tuner channel 2 SOFSync.
Parallel Data Input D3 or tuner channel 3 COF.
Parallel Data Input D2 or tuner channel 3 COFSync.
Parallel Data Input D1 or tuner channel 3 SOF.
Parallel Data Input D0 or tuner channel 3 SOFSync.
Parallel Data Input Dm1 for extended floating point input modes. Dm1 has internal weak pull-down.
Input enable for Parallel Data Input bus A. Active low. This pin enables the input to the part in one of two modes,
gated or interpolated. In gated mode, one sample is taken per CLK when ENI is asserted.
Input enable for Parallel Data Input bus B. Active low. This pin enables the input to the part in one of two modes,
gated or interpolated. In gated mode, one sample is taken per CLK when ENI is asserted.
Input enable for Parallel Data Input bus C. Active low. This pin enables the input to the part in one of two
modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENI is asserted.
Input enable for Parallel Data Input bus D. Active low. This pin enables the input to the part in one of two
modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENI is asserted.
-
-
-
Positive Power Supply Voltage (core), 2.5V
0.125
Positive Power Supply Voltage (I/O), 3.3V
0.165
Ground, 0V.
TYPE
DESCRIPTION
SYNCI0
SYNCI1
SYNCI2
I
I
I
FN6013 Rev.3.00
July 13, 2007
Page 4 of 65
ISL5216
Pin Descriptions
NAME
SYNCI3
SYNCO
I
O
(Continued)
DESCRIPTION
Synchronization input signal for channel 3. Same functions as SYNCI but connects only to channel 3. This pin
is internally pulled low to allow it to be left unconnected.
Synchronization Output Signal. The processing of multiple ISL5216 or HSP50216 devices can be
synchronized by tying the SYNCO from one ISL5216 device (the master) to the SYNCI of all the
ISL5216/HSP50216 devices (the master and slaves).
Reset Signal. Active low. Asserting reset will halt all processing and set certain registers to default values.
Test data out
Test data in. Contains weak internal pull-up.
Test mode select. Contains weak internal pull-up.
Test clock. Contains weak internal pull-down.
Test reset. Active low. Contains weak internal pull-down.
Serial Data Output 1A. A serial data stream output which can be programmed to consist of I1, Q1, I2, Q2,
magnitude, phase, frequency (d/dt), AGC gain, and/or zeros. In addition, data outputs from Channels 0, 1, 2
and 3 can be multiplexed into a common serial output data stream. Information can be sequenced in a
programmable order.
See Serial Data Output Formatter Section and Microprocessor Interface Section.
Serial Data Output 2A. This output is provided as an auxiliary output for Serial Data Output 1A to route data to
a second destination or to output two words at a time for higher sample rates. SD2A has the same
programmability as SD1A except that floating point format is not available.
See Serial Data Output Formatter
Section and Microprocessor Interface Section.
Serial Data Output 1B. See description for SD1A.
Serial Data Output 2B. See description for SD2A.
Serial Data Output 1C. See description for SD1A.
Serial Data Output 2C. See description for SD2A.
Serial Data Output 1D. See description for SD1A.
Serial Data Output 2D. See description for SD2A.
Serial Output Clock. Can be programmed to be at 1, 1/2, 1/4, 1/8, or 1/16 times the clock frequency. The
polarity of SCLK is programmable.
Serial Data Output 1A sync signal. This signal is used to indicate the start of a data word and/or frame of data.
The polarity and position of SYNCA is programmable.
Serial Data Output 1B sync signal. This signal is used to indicate the start of a data word and/or frame of data.
The polarity and position of SYNCB is programmable.
Serial Data Output 1C sync signal. This signal is used to indicate the start of a data word and/or frame of data.
The polarity and position of SYNCC is programmable.
Serial Data Output 1D sync signal. This signal is used to indicate the start of a data word and/or frame of data.
The polarity and position of SYNCD is programmable.
Microprocessor Interface Data bus.
See Microprocessor Interface Section.
P15 is the MSB.
Microprocessor Interface Address bus. ADD2 is the MSB.
See Microprocessor Interface Section.
Note: ADD2
is not
used but designated for future expansion.
Microprocessor Interface Write or Data Strobe Signal. When the Microprocessor Interface Mode Control,
P
MODE, is a low data transfers (from either P(15:0) to the internal write holding register or from the internal write
holding register to the target register specified) occur on the low to high transition of WR when CE is asserted
(low). When the
P
MODE control is high this input functions as a data read/write strobe. In this mode with
RD/WR low data transfers (from either P(15:0) to the internal write holding register or from the internal write
holding register to the target register specified) occur on the low to high transition of Data Strobe. With RD/WR
high the data from the address specified is placed on P(15:0) when Data Strobe is low.
See Microprocessor
Interface Section.
TYPE
RESET
JTAG
TDO
TDI
TMS
TCLK
TRST
OUTPUTS
SD1A
I
O
I
I
I
I
O
SD2A
O
SD1B
SD2B
SD1C
SD2C
SD1D
SD2D
SCLK
SYNCA
SYNCB
SYNCC
SYNCD
O
O
O
O
O
O
O
O
O
O
O
MICROPROCESSOR INTERFACE
P(15:0)
ADD(2:0)
WR
or
DSTRB
I/O
I
I
FN6013 Rev.3.00
July 13, 2007
Page 5 of 65
京公网安备 11010802033920号
EEWORLD
