Data Sheet
FEATURES
Fast and flexible output rate—5 SPS to 250 kSPS
Fast settling time—20 µs
Channel scan data rate of 50 kSPS/channel
Performance specifications
17 noise free bits at 250 kSPS
20 noise free bits at 2.5 kSPS
22 noise free bits at 5 SPS
INL ±2.5 ppm of FSR
85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
User-configurable input channels
2 fully differential or 4 pseudo differential
Crosspoint multiplexer
On-chip 2.5 V reference (drift 2 ppm/°C)
Internal oscillator, external crystal, or external clock
Power supply
Single supply: 5 V AVDD1, 2 V to 5 V AVDD2 and IOVDD
Optional split supply: AVDD1 and AVSS ± 2.5 V
Current: 7.8 mA
Temperature range: −40°C to +105°C
3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
CRC error checking
SPI, QSPI, MICROWIRE, and DSP compatible
24-Bit, 250 kSPS Sigma-Delta ADC
with 20 µs Settling
AD7176-2
GENERAL DESCRIPTION
The
AD7176-2
is a fast settling, highly accurate, high resolution,
multiplexed Σ-Δ analog-to-digital converter (ADC) for low band-
width input signals. Its inputs can be configured as two fully
differential or four pseudo differential inputs via the integrated
crosspoint multiplexer. An integrated precision, 2.5 V, low drift
(2 ppm/°C), band gap internal reference (with an output
reference buffer) adds functionality and reduces the external
component count.
The maximum channel scan data rate is 50 kSPS/channel
(settling time of 20 µs), resulting in fully settled data with
17 noise free bits. User-selectable output data rates range from
5 SPS to 250 kSPS. The resolution increases at lower speeds.
The
AD7176-2
offers three key digital filters. The fast settling
sinc5 + sinc1 filter maximizes the channel scan rate. The sinc3
filter maximizes the resolution for single-channel, low speed
applications. For 50 Hz and 60 Hz environments, the
AD7176-2
specific filter minimizes the settling times or maximizes the
rejection of the line frequency. These enhanced filters enable
simultaneous 50 Hz and 60 Hz rejection with a 27 SPS output
data rate (with a settling time of 36 ms).
System offset and gain errors can be corrected on a per channel
basis. This per channel configurability extends to the output data
rate used for each channel when using a sinc5 + sinc1 filter. All
switching of the crosspoint multiplexer is controlled by the ADC
and can be configured to automatically control an external
multiplexer via the GPIO pins.
The specified operating temperature range is −40°C to +105°C.
The
AD7176-2
is housed in a 24-lead TSSOP package.
IOVDD REGCAPD
BUFFERED
PRECISION
REFERENCE
INT
REF
CS
AIN1
AIN2
AIN3
AIN4
CROSSPOINT
MULTIPLEXER
AVSS
GPIO0 GPIO1
XTAL1 CLKIO/XTAL2
GPIO AND
MUX
I/O CONTROL
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
Σ-Δ ADC
DIGITAL
FILTER
SERIAL
INTERFACE
AND CONTROL
SCLK
DIN
DOUT/RDY
SYNC/ERROR
APPLICATIONS
Process control: PLC/DCS modules
Temperature and pressure measurement
Medical and scientific multichannel instrumentation
Chromatography
FUNCTIONAL BLOCK DIAGRAM
AVDD1
AVDD2 REGCAPA REF– REF+ REFOUT
1.8V
LDO
1.8V
LDO
AIN0
AD7176-2
DGND
11037-001
Figure 1.
Rev. D
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AD7176-2* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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REFERENCE MATERIALS
Press
• Analog Devices’ 24-bit Sigma-Delta A/D Converter
Achieves Twice the Speed of Competing Converters and
Industry’s Best Noise Performance
Technical Articles
•
Flexible Bandwidth 4 mA to 20 mA Current Input with
Easy HART Compatibility
Tutorials
•
MT-022: ADC Architectures III: Sigma-Delta ADC Basics
•
MT-023: ADC Architectures IV: Sigma-Delta ADC
Advanced Concepts and Applications
EVALUATION KITS
•
AD7176-2 Evaluation Board
DOCUMENTATION
Data Sheet
• AD7176-2: 24-Bit, 250 kSPS Sigma-Delta ADC with 20 μs
Settling Data Sheet
Technical Books
•
The Data Conversion Handbook, 2005
User Guides
• UG-478: Evaluation Board for the AD7176-2—24-Bit, 250
kSPS Sigma-Delta ADC with 20 μs Settling
DESIGN RESOURCES
•
AD7176-2 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
SOFTWARE AND SYSTEMS REQUIREMENTS
•
AD7176-2 FMC-SDP Interposer & Evaluation Board / Xilinx
KC705 Reference Design
•
AD717x Microcontroller No-OS
•
BeMicro FPGA Project for AD7176-2 with Nios driver
•
AD717x Eval+ Software
DISCUSSIONS
View all AD7176-2 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TOOLS AND SIMULATIONS
•
AD7176-2 Digital Filter Frequency Response Model
•
AD7176-2 IBIS Model
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
REFERENCE DESIGNS
•
CN0292
•
CN0310
•
CN0364
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AD7176-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Timing Characteristics ................................................................ 7
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 11
Noise Performance and Resolution .............................................. 17
Getting Started ................................................................................ 18
Power Supplies ............................................................................ 19
Digital Communication............................................................. 19
Configuration Overview ........................................................... 21
Circuit Description ......................................................................... 26
Analog Input ............................................................................... 26
Driver Amplifiers ....................................................................... 26
AD7176-2 Reference ................................................................... 29
AD7176-2 Clock Source ............................................................. 30
Digital Filters ................................................................................... 31
Sinc5 + Sinc1 Filter..................................................................... 31
Sinc3 Filter ................................................................................... 32
Single Cycle Settling ................................................................... 32
Enhanced 50 Hz and 60 Hz Rejection Filters ......................... 34
Operating Modes ............................................................................ 37
Continuous Conversion Mode ................................................. 37
Continuous Read Mode ............................................................. 38
Single Conversion Mode ........................................................... 39
Standby and Power-Down Modes ............................................ 40
Calibration Modes ...................................................................... 40
Digital Interface .............................................................................. 41
Checksum Protection................................................................. 41
CRC Calculation ......................................................................... 42
Integrated Functions ...................................................................... 44
General-Purpose I/O ................................................................. 44
External Multiplexer Control.................................................... 44
Data Sheet
Delay ............................................................................................ 44
16-Bit/24-Bit Conversions......................................................... 44
Serial Interface Reset (Dout_Reset) ......................................... 44
Synchronization (SYNC/ERROR) ........................................... 44
Error Flags ................................................................................... 45
DATA_STAT ............................................................................... 45
IOSTRENTGH ........................................................................... 45
Grounding and Layout .................................................................. 46
Register Summary .......................................................................... 47
Register Details ............................................................................... 49
Communications Register......................................................... 49
Status Register ............................................................................. 50
ADC Mode Register ................................................................... 51
Interface Mode Register ............................................................ 52
Register Check ............................................................................ 53
Data Register ............................................................................... 53
GPIO Configuration Register ................................................... 54
ID Register................................................................................... 55
Channel Map Register 0 ............................................................ 56
Channel Map Register 1 ............................................................ 57
Channel Map Register 2 ............................................................ 58
Channel Map Register 3 ............................................................ 59
Setup Configuration Register 0 ................................................ 60
Setup Configuration Register 1 ................................................ 60
Setup Configuration Register 2 ................................................ 61
Setup Configuration Register 3 ................................................ 61
Filter Configuration Register 0................................................. 62
Filter Configuration Register 1................................................. 63
Filter Configuration Register 2................................................. 64
Filter Configuration Register 3................................................. 65
Offset Register 0 ......................................................................... 66
Offset Register 1 ......................................................................... 66
Offset Register 2 ......................................................................... 66
Offset Register 3 ......................................................................... 66
Gain Register 0............................................................................ 67
Gain Register 1............................................................................ 67
Gain Register 2............................................................................ 67
Gain Register 3............................................................................ 67
Outline Dimensions ....................................................................... 68
Ordering Guide .......................................................................... 68
Rev. D | Page 2 of 68
Data Sheet
REVISION HISTORY
3/16—Rev. C to Rev. D
Changes to Power Supplies Section ..............................................19
Added AD7176-2 Reset Section ....................................................20
6/15—Rev. B to Rev. C
Changes to Figure 8 ........................................................................11
10/14—Rev. A to Rev. B
Changes to General Description ..................................................... 1
Changes to Figure 1 .......................................................................... 1
Changes to Table 1 ............................................................................ 4
Added ESD Rating (HBM) of 3.5 kV; Table 3 and Changes
to Table 4 ............................................................................................ 8
Changes to Figure 5 to Figure 10 Captions..................................11
Changes to Figure 11 to Figure 16 Captions ...............................12
Changes to Figure 17 to Figure 22 Captions ...............................13
Changes to Figure 23 Caption; Added Figure 24 to Figure 28;
Renumbered Sequentially ..............................................................14
Added Figure 29 to Figure 34 ........................................................15
Added Figure 35 to Figure 36 ........................................................16
Changes to Noise Performance and Resolution Section ............17
Changes to Getting Started Section and Figure 37 .....................18
Changes to Configuration Overview Section ..............................21
Changes to Digital Filters Section and Table 19..........................31
Changes to Sinc3 Filter Section .....................................................32
Changes to Table 20 ........................................................................33
AD7176-2
Reordered Figure 56 to Figure 63 ................................................. 35
Changes to Figure 65 ...................................................................... 38
Changes to Standby and Power-Down Modes Section .............. 40
Changes to Digital Interface Section and Figure 68 ................... 41
Changes to CRC Calculation Example ......................................... 42
Added Integrated Function Section and Delay Section; Changes
to General-Purpose I/O Section and Normal Synchronization
Section .............................................................................................. 44
Changed Register 0x02 Bits[2:1] to HIDE_DELAY ................... 47
Changes to Table 23 ........................................................................ 49
Changes to Table 26 ........................................................................ 52
Changes to Table 29 ........................................................................ 54
Changes to Table 31 ........................................................................ 56
Changes to Table 32 ........................................................................ 57
Changes to Table 33 ........................................................................ 58
Changes to Table 34 ........................................................................ 59
Changes to Table 39 ........................................................................ 62
Changes to Table 40 ........................................................................ 63
Changes to Table 41 ........................................................................ 64
Changes to Table 42 ........................................................................ 65
4/13—Rev.0 to Rev. A
Changes to Table 20 ........................................................................ 31
11/12—Revision 0—Initial Version
Rev. D | Page 3 of 68
AD7176-2
SPECIFICATIONS
Data Sheet
AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS,
internal master clock = 16 MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
ADC SPEED AND PERFORMANCE
Output Data Rate (ODR)
No Missing Codes
1
Resolution
Noise
Noise Free Resolution
Test Conditions/Comments
Min
5
24
Typ
Max
250,000
Unit
SPS
Bits
Excluding sinc3 filter ≥125 kSPS
See Table 6
See Table 6
Sinc5 + sinc1 filter (default)
250 kSPS, REF+ = 5 V
2.5 kSPS, REF+ = 5 V
5 SPS, REF+ = 5 V
2.5 V reference
5 V reference
Internal short
Internal short
17.3
20.1
22.4
±2.5
±7
±40
±110
±450
±10
±0.5
±3
±7
Bits
Bits
Bits
ppm of FSR
ppm of FSR
µV
nV/°C
nV/1000
hours
ppm/FSR
ppm/FSR/°C
ppm/FSR/
1000 hours
dB
dB
dB
ACCURACY
Integral Nonlinearity (INL)
Offset Error
2
Offset Drift
Offset Drift vs. Time
3
Gain Error
2
Gain Drift vs. Temperature
1
Gain Drift vs. Time
3
REJECTION
Power Supply Rejection
Common-Mode Rejection
At DC
At 50 Hz and 60 Hz
1
Normal Mode Rejection
1
25°C
±50
±1
AVDD1, AVDD2 V
IN
= 1 V
V
IN
= 0.1 V
20 SPS ODR (post filter)
(50 Hz ± 1 Hz and 60 Hz ± 1 Hz)
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
Internal clock, 20 SPS ODR (post filter)
External clock, 20 SPS ODR (post filter)
95
130
90
71
85
90
90
±V
REF
dB
dB
V
V
µA/V
nA/V/°C
nA/V/°C
dB
ANALOG INPUTS
Differential Input Voltage Range
Absolute AIN Voltage Limits
1
Analog Input Current
Input Current
Input Current Drift
Crosstalk
INTERNAL REFERENCE
Output Voltage
Initial Accuracy
1
Temperature Coefficient
AVSS − 0.050
±48
±0.75
±4
−120
AVDD1 + 0.05
External clock
Internal clock (±2.5 % clock)
1 kHz input
100 nF external capacitor on REFOUT
to AVSS
REFOUT with respect to AVSS
T
A
= 25°C
4
0°C to +105°C
−40°C to +105°C
I
L
AVDD1 and AVDD2
∆V
OUT
/∆I
L
e
N
, 0.1 Hz to 10 Hz
e
N
, 1 kHz
100 nF capacitor
2.5
− 0.16%
±2
±3
−10
93
32
4.5
215
60
+ 0.16%
±5
±10
+10
V
V
ppm/°C
ppm/°C
mA
dB
ppm/mA
µV rms
nV/√Hz
µs
Reference Load Current, I
LOAD
Power Supply Rejection (Line
Regulation)
Load Regulation
Voltage Noise
Voltage Noise Density
Turn-On Settling Time
Rev. D | Page 4 of 68
Embedded System
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