EEWORLDEEWORLDEEWORLD

Part Number

Search

DAFIR-GEN-X2-U2

Description
Development Software DIST ARITH FIR FILTR Generator (XP2)
CategoryDevelopment board/suite/development tools   
File Size34KB,3 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Download Datasheet Parametric View All

DAFIR-GEN-X2-U2 Online Shopping

Suppliers Part Number Price MOQ In stock  
DAFIR-GEN-X2-U2 - - View Buy Now

DAFIR-GEN-X2-U2 Overview

Development Software DIST ARITH FIR FILTR Generator (XP2)

DAFIR-GEN-X2-U2 Parametric

Parameter NameAttribute value
Product CategoryDevelopment Software
ManufacturerLattice
Moisture SensitiveYes
PackagingBulk
Factory Pack Quantity1
Distributed Arithmetic FIR (DA-FIR)
Page 1 of 3
Home
>
Products
>
Intellectual Property
>
Lattice IP Cores
> Distributed Arithmetic FIR (DA-FIR)
Distributed Arithmetic FIR (DA-FIR) Filter Generator
Overview
The Lattice Distributed Arithmetic Finite Impulse Response (DA-FIR) Filter Generator IP
implements a highly configurable, multi-channel DA-FIR filter, using distributed
arithmetic algorithms implemented in FPGA Look Up Table (LUT) or Embedded Block
Memory (EBR) to efficiently support the sum-of-product calculations required to perform
the filter function. These techniques generate very area-efficient utilization of the FPGA
LUTs while enabling savings of multiply-accumulate blocks (sysDSP) for other design logic. As a result, the DA-FIR Filter
Generator IP core is extremely useful for implementing custom DSP blocks in Lattice FPGAs. Please refer to the user's guide to
determine which cores are available for each device family.
Features
Variable number of taps up to 1024
Multi-channel support (up to 32 channels)
Polyphase interpolation/decimation filters
Halfband filters
Interpolation and Decimation ratios from 2 to 32
Input data widths from 4 to 32 bits
Coefficient widths from 4 to 32 bits
Signed or unsigned data and coefficients
Selectable rounding: truncation, rounding away from zero,
convergent rounding
Optional saturation logic for overflow handling
Full precision arithmetic
Specification of fractional inputs and outputs
Support for both serial and parallel filters, with user
specified degree of parallelism.
Configurable pipelining to increase performance
Optimizations based on filter characteristics (symmetry and
halfband).
Handshake signals to facilitate smooth interfacing
Performance and Resource Utilization
LatticeECP3
1
Channels
1
1
1
Taps
16
9
36
Interpolation
Disable
Disable
Enable
DWidth
16
8
12
Round
TRUN
TRUN
TRUN
SLICEs
290
512
600
LUTs
348
611
709
EBRs
-
-
-
Registers
476
877
883
Fmax
318
279
308
1. Performance and utilization data are generated targeting a LFE3-70E-7FN484CES device using Lattice Diamond 1.0 and Synplify Pro D-
2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade
within the LatticeECP3 family.
LatticeECP2M/S
Channels
1
1
Taps
16
9
Interpolation
Disable
Disable
DWidth
16
8
Round
TRUN
TRUN
1
SLICEs
317
550
LUTs
378
655
EBRs
-
-
Registers
481
887
Fmax
343
310
http://www.latticesemi.com/products/intellectualproperty/ipcores/distributedarithmeticfir...
10/10/2011
[Transfer] A great guy introduces you to "Signals and Systems"
[p=19, null, left][size=13px][b]Lesson 1 What is convolution? What is the use of convolution? What is Fourier transform? What is Laplace transform? [/b][/size][/p] [p=19, null, left][size=13px]Introdu...
dontium ADI Reference Circuit
The 128 storage units in the 80C51 microcontroller's on-chip RAM are divided into which four main parts? What are the main functions of each part?
The 128 storage units in the 80C51 microcontroller's on-chip RAM are divided into which four main parts? What are the main functions of each part?...
STORMc Microchip MCU
Test and diagnosis system for second-line detection and maintenance of passive interference equipment
Based on PXI bus and LabVIEW technology, a passive interference equipment test and diagnosis system wasbuilt , which can complete the rapid and accurate testing of various functions and performance pa...
sairvee Test/Measurement
DSP28335+AIC23 can send and receive data, but the data seems wrong and sounds like all noise. Is it a hardware problem?
The hardware I am using now is the development board of Yanxu. The software is Interfacing the TMS320F2833x to the AIC23B Stereo Audio Codec.zip provided by TI. I modified the control interface and da...
ayu_ag DSP and ARM Processors
34063 5V to 12V
is such a circuit diagram. It can reach 12v in Proteus, but why is it only 4.3v in reality? I have done it twice on the perf board and both times were 4.3. The parameters were also obtained from the w...
fadeon Power technology
List of original electronic competitions over the years
[i=s] This post was last edited by paulhyde on 2014-9-15 09:12 [/i] List of original electronic competitions over the years...
279111429 Electronics Design Contest

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 712  1567  1067  1034  110  15  32  22  21  3 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号