Table 4. CDB4391 Jumper and Switch settings - CONTOL PORT MODE..................................... 7
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I
2
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Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
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2
DS335DB2
CDB4391
1. CDB4391 SYSTEM OVERVIEW
The CDB4391 evaluation board is an excellent
means of quickly evaluating the CS4391. The
CS8414 digital audio interface receiver provides an
easy interface to digital audio signal sources in-
cluding the majority of digital audio test equip-
ment. The evaluation board also allows the user to
supply clocks and data through a 10-pin header for
system development.
The CDB4391 schematic has been partitioned into
9 schematics shown in Figures 2 through 10. Each
partitioned schematic is represented in the system
diagram shown in Figure 1. Notice that the system
diagram also includes the interconnections be-
tween the partitioned schematics.
datasheet. It is likely that the de-emphasis control
for the CS4391 will be erroneous and produce an
incorrect audio output if the Error Information
Switch is activated and the CS4391 is in the stand-
alone mode with internal serial clock mode select-
ed.
Encoded sample frequency information can be dis-
played provided a proper clock is being applied to
the FCK pin of the CS8414. When an LED is lit,
this indicates a "1" on the corresponding pin locat-
ed on the CS8414. When an LED is off, this indi-
cates a "0" on the corresponding pin. Neither the L
nor R option of CSLR/FCK should be selected if
the FCK pin is being driven by a clock signal.
The evaluation board has been designed such that
the input can be either optical or coax, see Figure 6.
However, both inputs cannot be driven simulta-
neously.
2. CS4391 DIGITAL TO ANALOG
CONVERTER
A description of the CS4391 is included in the
CS4391 datasheet.
4. CS8414 DATA FORMAT
The CS8414 data format can be set with switches
M0, M1, M2, and M3, as described in the CS8414
datasheet. The format selected must be compatible
with the data format of the CS4391, as shown in the
CS4391 datasheet. Please note that the CS8414
does not support all the possible modes of the
CS4391 and the Left-Justified Format for the
CS8414 and the CS4391 have incompatible serial
clocks, see Table 1. The default settings for M0-M3
on the evaluation board are given in Tables 3-4.
CS4391 CP Mode
Format
0
1
2
3
4
5
CS4391 SA
Mode Format
0
1
2
3
-
-
CS8414
Format
Unsupported
2
5
Unsupported
Unsupported
6
3. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard
S/PDIF data format using a CS8414 Digital Audio
Receiver, Figure 5. The outputs of the CS8414 in-
clude a serial bit clock, serial data, left-right clock
(FSYNC), de-emphasis control and a 256 Fs mas-
ter clock. The operation of the CS8414 and a dis-
cussion of the digital audio interface are included in
the CS8414 datasheet.
During normal operation, the CS8414 operates in
the Channel Status mode where the LED’s display
channel status information for the channel selected
by the CSLR/FCK jumper. This allows the CS8414
to decode the de-emphasis bit from the digital au-
dio interface for control of the CS4391 de-empha-
sis filter, when the CS4391 is in stand-alone mode.
When the Error Information Switch is activated,
the CS8414 operates in the Error and Frequency in-
formation mode. The information displayed by the
LED’s can be decoded by consulting the CS8414
Table 1. CS8414 Supported Formats
DS335DB2
3
CDB4391
5. INPUT/OUTPUT FOR CLOCKS AND
DATA
The evaluation board has been designed to allow
interfacing to external systems via the 10-pin head-
er, J9. This header allows the evaluation board to
accept externally generated clocks and data. The
schematic for the clock/data I/O is shown in
Figure 9. The 74HC243 transceiver functions as an
I/O buffer where HRD1 through HRD6 determine
if the transceiver operates as a transmitter or receiv-
er. A transmit function is implemented with all
jumpers, HRD1 through HDR6 in the 8414 posi-
tion. LRCK, SDATA, and SCLK from the CS8414
will be outputs on J9. The transceiver operates as a
receiver with HRD1 through HDR6 in the
EXT_CLK position. MCLK, LRCK, SDATA and
SCLK on J9 become inputs.
7. GROUNDING AND POWER SUPPLY
DECOUPLING
The CS4391 requires careful attention to power
supply and grounding arrangements to optimize
performance. Figure 10 details the power distribu-
tion used on this board. The decoupling capacitors
are located as close to the CS4391 as possible. Ex-
tensive use of ground plane fill in the evaluation
board yields large reductions in radiated noise.
8. CONTROL PORT SOFTWARE
The CDB4391 is shipped with Windows based
software for interfacing with the CS4391 control
port via the DB25 connector, P1. The software can
be used to communicate with the CS4391 in either
SPI
or I
2
C
mode; however, in SPI mode the
CS4391 registers are write-only. Note: The
CDB4391 must be configured for control port
mode as shown in Table 4.
Further documentation for the software is available
on the distribution diskette. The documentation is
available in the plain text format file,
README.TXT.
6. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by six
binding posts (GND, +5V, +3/+5V, VL, VCC and
VEE), see Figure 10. The +5V input supplies pow-
er to the +5 volt digital circuitry (VA+5, VD+5,
VDPC+5), while the VL input supplies power to
the Voltage Level Converters and the CS4391
VL pin. +3/+5V supplies power to the CS4391.
VCC and VEE supply power to the op-amp and can
be +/-5 to +/-12 volts.
WARNING:
Refer to the CS4391 datasheet for
maximum allowable voltages levels. Operation
outside of this range can cause permanent damage
to the device.
9. DSD OPERATION
The CDB4391 supports Direct Stream Digital
(DSD) operation through the header for external
clocks and data, J9. The CS4391 must be placed
into the DSD mode and the jumpers HDR1 through
HDR6 must be placed into the external clock posi-
tions.
4
DS335DB2
CDB4391
CONNECTOR
+5V
+3/+5V
V
L
V
EE
V
CC
GND
Coax Input
Optical Input
J9
Parallel Port
HDR9
AOUTA
AOUTB
INPUT/OUTPUT
Input
Input
Input
Input
Input
Input
Input
Input
Input/Output
Input/Output
Input/Output
Output
Output
+ 5 Volt power
SIGNAL PRESENT
+ 2.7 to + 5.5 Volt power for the CS4391
+ 1.8 to +5.5 digital interface voltage (Note that V
L
should not
exceed the voltage applied to the+3/+5V terminal)
-12 to -5V negative supply for the op-amp
+5 to +12V positive supply for the op-amp
Ground connection from power supply
Digital audio interface input via coax
Digital audio interface input via optical
I/O for master, serial, left/right clocks and serial data
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