Data Sheet
FEATURES
Analog variable gain range: −12 dB to +22 dB
Linear-in-dB scaling: 37.5 dB/V
3 dB bandwidth: 800 MHz @ V
GAIN
= 0.5 V
Integrated rms detector
P1dB: 16 dBm @ 140 MHz
Output IP3: 33 dBm @ 140 MHz
Noise figure at maximum gain: 9.5 dB @ 140 MHz
Input and output impedances: 50 Ω
Single-supply voltage from 4.5 V to 5.5 V
RoHS-compliant, 24-lead LFCSP
ICOM
16
OCOM
6
GAIN
1
OCOM
7
10
800 MHz, Linear-in-dB
VGA with AGC Detector
AD8368
FUNCTIONAL BLOCK DIAGRAM
VPSO
MODE
21
VPSO VPSI VPSI VPSI VPSI VPSI
9
11
12
22
23
13
AD8368
GAIN INTERPOLATOR
g
m
STAGES
0dB –2dB
–4dB
–36dB
REF
50Ω
DECL
ATTENUATOR LADDER
2
–
FIXED-GAIN
AMPLIFIER
OUTPUT
BUFFER
24
8
3
4
14
15
ENBL
OUTP
HPFL
DECL
DECL
DECL
INPT
19
ICOM
17
ICOM
18
ICOM
20
X
2
+
5
APPLICATIONS
Complete IF AGC amplifiers
Gain trimming and leveling
Cellular base stations
Point-to-point radio links
RF instrumentation
Figure 1.
DETO
DETI
GENERAL DESCRIPTION
The AD8368 is a variable gain amplifier (VGA) with analog
linear-in-dB gain control that can be used from low frequencies
to 800 MHz. Its excellent gain range, conformance, and flatness
are attributed to the Analog Devices, Inc., X-AMP® architecture,
an innovative technique for implementing high performance
variable gain control.
The gain range of −12 dB to +22 dB is scaled accurately to
37.5 dB/V with excellent conformance error. The AD8368 has
a 3 dB bandwidth of 800 MHz that is nominally independent
of gain setting. At 140 MHz, the OIP3 is 33 dBm at maximum
gain. The output noise floor is −143 dBm/Hz, which corresponds
to a 9.5 dB noise figure at maximum gain. The single-ended
input and output impedances are nominally 50 Ω.
The gain of the AD8368 can be configured to be an increasing
or decreasing function of the gain control voltage depending
on whether the MODE pin is pulled to the positive supply or
to ground, respectively. When MODE is pulled high, the
AD8368 operates as a typical VGA with increasing gain.
By connecting MODE to ground and using the on-board rms
detector, the AD8368 can be configured as a complete
automatic gain control (AGC) system with RSSI. The output
power is accurately leveled to the internal default setpoint of
63 mV rms (−11 dBm referenced to 50 Ω), independent of the
waveform crest factor. Because the uncommitted detector
input is available at DETI, the AGC loop can level the signal at
the AD8368 output or at any other point in the signal chain
over a maximum input power range of 34 dB. Furthermore, the
setpoint level can be raised by dividing down the output signal
before applying it to the detector.
The AD8368 operates from a supply voltage of 4.5 V to 5.5 V
and consumes 60 mA of current. It can be fully powered down
to <3 mA by grounding the ENBL pin. The AD8368 is fabricated
using the Analog Devices proprietary SiGe SOI complementary
bipolar IC process. It is available in a 24-lead LFCSP and
operates over the industrial temperature range of −40°C to
+85°C. Application boards are available upon request.
Rev. C
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AD8368* PRODUCT PAGE QUICK LINKS
Last Content Update: 09/21/2017
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REFERENCE MATERIALS
Product Selection Guide
•
RF Source Booklet
•
Variable Gain Amplifier Selection Table
EVALUATION KITS
•
AD8368 Evaluation Board
DESIGN RESOURCES
DOCUMENTATION
Data Sheet
•
AD8368: 800 MHz, Linear-in-dB VGA with AGC Detector
Data Sheet
•
AD8368 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
TOOLS AND SIMULATIONS
• ADIsimPLL™
•
ADIsimRF
DISCUSSIONS
View all AD8368 EngineerZone Discussions.
REFERENCE DESIGNS
•
CN0072
•
CN0340
•
CN0360
SAMPLE AND BUY
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AD8368
TABLE OF CONTENTS
Features ............................................................................................ 1
Applications ..................................................................................... 1
Functional Block Diagram ............................................................ 1
General Description ....................................................................... 1
Revision History ............................................................................. 2
Specifications................................................................................... 3
Absolute Maximum Ratings .......................................................... 5
ESD Caution ................................................................................ 5
Pin Configuration and Function Descriptions ........................... 6
Typical Performance Characteristics ........................................... 7
Circuit Description ....................................................................... 12
Input Attenuator and Interpolator ......................................... 12
Data Sheet
Fixed-Gain Stage and Output Buffer ..................................... 12
Output Offset Correction........................................................ 12
Input and Output Impedances ............................................... 12
Gain Control Interface ............................................................ 13
Applications Information ............................................................ 14
VGA Operation ........................................................................ 14
AGC Operation ........................................................................ 14
Stability and Layout Considerations ...................................... 16
Evaluation Board .......................................................................... 17
Outline Dimensions ..................................................................... 19
Ordering Guide ........................................................................ 19
REVISION HISTORY
9/2017—Rev. B to Rev. C
Changed CP-24-3 to CP-24-7 ...................................... Throughout
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
9/2008—Rev. A to Rev. B
Added Stability and Layout Considerations Section ................. 16
Changes to Evaluation Board Section, Figure 40, and
Table 6 .............................................................................................. 17
Added Figure 41, Figure 42, Figure 43, and Figure 44;
Renumbered Sequentially.............................................................. 18
Added Exposed Pad Notation to Outline Dimensions ............. 19
10/2007—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3
Changes to Figure 4 to Figure 6 ...................................................... 7
Changes to Figure 16 ........................................................................ 9
Changes to Figure 31 ...................................................................... 12
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
4/2006—Revision 0: Initial Version
Rev. C | Page 2 of 20
Data Sheet
SPECIFICATIONS
V
S
= 5 V, T
A
= 25°C, system impedance Z
0
= 50 Ω, V
MODE
= 5 V, RF input = 140 MHz, unless otherwise noted.
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range
Maximum Input
Maximum Output
1
AC Input Impedance
AC Output Impedance
GAIN CONTROL INTERFACE (GAIN)
Gain Span
Gain Scaling
Gain Accuracy
Maximum Gain
Minimum Gain
V
GAIN
Range
Gain Step Response
Gain Input Bias Current
f = 70 MHz
Noise Figure
Output IP3
Output P1dB
1
f = 140 MHz
Noise Figure
Output IP3
Output P1dB
1
f = 240 MHz
Noise Figure
Output IP3
Output P1dB
1
f = 380 MHz
Noise Figure
Output IP3
Output P1dB
1
1
AD8368
Min
LF
Typ
Max
800
Unit
MHz
V
P
V
P
Ω
Ω
dB
dB/V
dB/V
dB
dB
dB
V
ns
µA
dB
dBm
dBm
dB
dBm
dBm
dB
dBm
dBm
dB
dBm
dBm
Conditions
3 dB bandwidth
To avoid input overload
To avoid clipping
From INPT to ICOM
From OUTP to OCOM
3
2
50
50
34
37.5
−38
±0.4
22
−12
0
100
−2
9.5
34
16
9.5
33
16
9.7
33
15
10
29
13
1
V
MODE
= 5 V, 50 mV
≤
V
GAIN
≤
950 mV
V
MODE
= 0 V, 50 mV
≤
V
GAIN
≤
950 mV
100 mV
≤
V
GAIN
≤
900 mV
V
GAIN
= 1 V
V
GAIN
= 0 V
For 6 dB gain step
Maximum gain
f
1
= 70 MHz, f
2
= 71 MHz, V
GAIN
= 1 V, 0 dBm per output tone
V
GAIN
= 0 V, V
MODE
= 0 V
Maximum gain
f
1
= 140 MHz, f
2
= 141 MHz, V
GAIN
= 1 V, 0 dBm per output tone
V
GAIN
= 0 V, V
MODE
= 0 V
Maximum gain
f
1
= 240 MHz, f
2
= 241 MHz, V
GAIN
= 1 V, 0 dBm per output tone
V
GAIN
= 0 V, V
MODE
= 0 V
Maximum gain
f
1
= 380 MHz, f
2
= 381 MHz, V
GAIN
= 1 V, 0 dBm per output tone
V
GAIN
= 0 V, V
MODE
= 0 V
Operation at compression is not recommended due to adverse distortion components.
Rev. C | Page 3 of 20
AD8368
V
S
= 5 V, T
A
= 25°C, system impedance Z
0
= 50 Ω, V
MODE
= 5 V, RF input = 140 MHz, unless otherwise noted.
Table 2.
Parameter
SQUARE LAW DETECTOR (DETI, DETO)
Output Setpoint
DETI DC Bias Level to ICOM
DETI Impedance
DETO Output Range
1
AGC Step Response
MODE CONTROL INTERFACE (MODE)
MODE Threshold
MODE Input Bias Current
POWER INTERFACE (VPSI, VPSO)
Supply Voltage
Total Supply Current
Disable Current
ENABLE INTERFACE (ENBL)
Enable Threshold
Enable Response Time
Min
Typ
−11
V
S
/2
710
0.6
0.1
30
3.5
50
4.5
5
60
2
2.5
1.5
3
ENBL Input Bias Current
1
Data Sheet
Max
Unit
dBm
V
Ω
pF
V
µs
V
µA
V
mA
mA
V
µs
µs
Conditions
OUTP connected to DETI
V
S
/2
For −6 dB input power step (C
DETO
= 1 nF)
5.5
ENBL high
ENBL low
150
µA
Time delay following off-to-on transition until output
reaches 90% of final value
Time delay following on-to-off transition until supply
current is less than 5 mA
V
ENBL
= 5 V
Refer to
AGC Operation
section.
Rev. C | Page 4 of 20
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