DAFIR-GEN-X2-UT1 datasheet, PDF

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DAFIR-GEN-X2-UT1: DescriptionDevelopment Software DIST ARITH FIR FILTER GENERATOR; CategoryDevelopment board/suite/development tools; File Size34KB，3 Pages; ManufacturerLattice; Websitehttp://www.latticesemi.com

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DAFIR-GEN-X2-UT1 Overview

Development Software DIST ARITH FIR FILTER GENERATOR

DAFIR-GEN-X2-UT1 Parametric

Parameter Name	Attribute value
Product Category	Development Software
Manufacturer	Lattice
RoHS	Details
Moisture Sensitive	Yes
Factory Pack Quantity	1

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Distributed Arithmetic FIR (DA-FIR)

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Home

Products

Intellectual Property

Lattice IP Cores

> Distributed Arithmetic FIR (DA-FIR)

Distributed Arithmetic FIR (DA-FIR) Filter Generator

Overview

The Lattice Distributed Arithmetic Finite Impulse Response (DA-FIR) Filter Generator IP

implements a highly configurable, multi-channel DA-FIR filter, using distributed

arithmetic algorithms implemented in FPGA Look Up Table (LUT) or Embedded Block

Memory (EBR) to efficiently support the sum-of-product calculations required to perform

the filter function. These techniques generate very area-efficient utilization of the FPGA

LUTs while enabling savings of multiply-accumulate blocks (sysDSP) for other design logic. As a result, the DA-FIR Filter

Generator IP core is extremely useful for implementing custom DSP blocks in Lattice FPGAs. Please refer to the user's guide to

determine which cores are available for each device family.

Features

Variable number of taps up to 1024

Multi-channel support (up to 32 channels)

Polyphase interpolation/decimation filters

Halfband filters

Interpolation and Decimation ratios from 2 to 32

Input data widths from 4 to 32 bits

Coefficient widths from 4 to 32 bits

Signed or unsigned data and coefficients

Selectable rounding: truncation, rounding away from zero,

convergent rounding

Optional saturation logic for overflow handling

Full precision arithmetic

Specification of fractional inputs and outputs

Support for both serial and parallel filters, with user

specified degree of parallelism.

Configurable pipelining to increase performance

Optimizations based on filter characteristics (symmetry and

halfband).

Handshake signals to facilitate smooth interfacing

Performance and Resource Utilization

LatticeECP3

Channels

Taps

Interpolation

Disable

Enable

DWidth

Round

TRUN

SLICEs

290

512

600

LUTs

348

611

709

EBRs

Registers

476

877

883

Fmax

318

279

308

1. Performance and utilization data are generated targeting a LFE3-70E-7FN484CES device using Lattice Diamond 1.0 and Synplify Pro D-

2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade

within the LatticeECP3 family.

LatticeECP2M/S

Channels

Taps

Interpolation

Disable

DWidth

Round

TRUN

SLICEs

317

550

LUTs

378

655

EBRs

Registers

481

887

Fmax

343

310

http://www.latticesemi.com/products/intellectualproperty/ipcores/distributedarithmeticfir...

10/10/2011

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