DS1996L-F5 datasheet, PDF - EEWORLD Datasheet

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DS1996L-F5: DescriptioniButtons; Categorystorage storage; File Size440KB，19 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1996L-F5 Overview

iButtons

DS1996L-F5 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Maxim
package instruction	MICROCAN-2
Contacts	2
Reach Compliance Code	not_compliant
Maximum access time	15000 ns
JESD-30 code	O-MEDB-N2
memory density	65536 bit
Memory IC Type	MEMORY CIRCUIT
memory width	1
Number of functions	1
Number of terminals	2
word count	65536 words
character code	64000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature	-40 °C
organize	64KX1
Package body material	METAL
Encapsulate equivalent code	BUTTON,.68IN
Package shape	ROUND
Package form	DISK BUTTON
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/5 V
Certification status	Not Qualified
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal location	END
Maximum time at peak reflow temperature	NOT SPECIFIED

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AVAILAB

DS1996

64Kb Memory iButton

SPECIAL FEATURES



65,536 bits of read/write nonvolatile memory

Overdrive mode boosts communication

speed to 142 kbits per second

256-bit scratchpad ensures integrity of data

transfer

Memory partitioned into 256-bit pages for

packetizing data

Data integrity assured with strict read/write

protocols

Operating temperature range from -40°C to

+70°C

Over 10 years of data retention

F5 MICROCAN

5.89

0.51



16.25

000000FBC52B



1-Wire



17.35

DATA

GROUND

All dimensions are shown in millimeters



Durable stainless steel case engraved with

registration number withstands harsh

environments

Easily affixed with self-stick adhesive

backing, latched by its flange, or locked with

a ring pressed onto its rim

Presence detector acknowledges when reader

first applies voltage

COMMON iButton FEATURES



Unique, factory-lasered and tested 64-bit

registration number (8-bit family code + 48-

bit serial number 8-bit CRC tester) assures

absolute traceability because no two parts are

alike

Multidrop controller for MicroLAN

Digital identification and information by

momentary contact

Chip-based data carrier compactly stores

Functional Diagrams

information

Data can be accessed while affixed to object

Economically communicates to bus master

with a single digital signal at 16.3 kbits per

second

Standard 16 mm diameter and 1-Wire

protocol ensure compatibility with iButton

family

Button shape is self-aligning with cup-

shaped probes



ORDERING INFORMATION

TEMP

PIN-

RANGE

PACKAGE

DS1996L-F5+

F5 MicroCan

-40°C to +70°C

+Denotes

a lead(Pb)-free/RoHS-compliant package.

PART

EXAMPLES OF ACCESSORIES

DS9096P

DS9101

DS9093RA

DS9093F

DS9092

Self-Stick Adhesive Pad

Multi-Purpose Clip

Mounting Lock Ring

Snap-In Fob

iButton Probe

iButton and 1-Wire are registered trademarks of Maxim Integrated Products, Inc.

Pin Configurations appear at end of data sheet.

Functional Diagrams continued at end of data sheet.

UCSP is a trademark of Maxim Integrated Products, Inc.

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

19-4896; Rev 8/09

DS1996

iButton DESCRIPTION

The DS1996 Memory iButton is a rugged read/write data carrier that acts as a localized database that can

be easily accessed with minimal hardware. The nonvolatile memory offers a simple solution to storing

and retrieving vital information pertaining to the object to which the iButton is attached. Data is

transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return.

The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to

the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command

will transfer the data to memory. This process ensures data integrity when modifying the memory. A

48-bit serial number is factory lasered into each DS1996 to provide a guaranteed unique identity which

allows for absolute traceability. The durable MicroCan package is highly resistant to environmental

hazards such as dirt, moisture, and shock. Its compact button-shaped profile is self-aligning with mating

receptacles, allowing the DS1996 to be easily used by human operators. Accessories permit the DS1996

to be mounted on almost any surface including plastic key fobs, photo-ID badges and printed circuit

boards. Applications include access control, work-in-progress tracking, electronic travelers, storage of

calibration constants, and debit tokens.

OVERVIEW

The block diagram in Figure 1 shows the relationships between the major control and memory sections of

the DS1996. The DS1996 has three main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad

and 3) 65536-bit SRAM. The hierarchal structure of the 1-Wire protocol is shown in Figure 2. The bus

master must first provide one of the six ROM Function Commands, 1)Read ROM, 2) Match ROM, 3)

Search ROM, 4) Skip ROM, 5) Overdrive-Skip ROM or Overdrive-Match ROM. Upon completion of an

overdrive ROM command byte executed at regular speed, the device will enter Overdrive mode where all

subsequent communication occurs at a higher speed. The protocol required for these ROM Function

Commands is described in Figure 9. After a ROM Function Command is successfully executed, the

memory functions become accessible and the master may provide any one of the four memory function

commands. The protocol for these memory function commands is described in Figure 7. All data read and

written least significant bit first.

PARASITE POWER

The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry ”steals” power

whenever the data line is high. The data line will provide sufficient power as long as the specified timing

and voltage requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this

input, battery power is not consumed for 1-Wire ROM function commands, and 2) if the battery is

exhausted for any reason, the ROM may still be read normally. The remaining circuitry of the DS1996 is

solely operated by battery energy.

64-BIT LASERED ROM

Each DS1996 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.

The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (Figure 3.)

The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates

as shown in Figure 4. The polynomial is X

+ X

+ 1. Additional information about the Dallas 1-

Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards.

The shift register bits are initialized to zero. Then starting with the least significant bit of the family code,

1 bit at a time is shifted in. After the 8

bit of the family code has been entered, then the serial number is

entered. After the 48

bit of the serial number has been entered, the shift register contains the CRC

value. Shifting in the 8 bits of CRC should return the shift register to all zeros.

2 of 19

DS1996

MEMORY

The memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages

called memory. The DS1996 contains 256 pages which comprise the 65536-bit SRAM. The scratchpad is

an additional page that acts as a buffer when writing to memory.

ADDRESS REGISTERS AND TRANSFER STATUS

Because of the serial data transfer, the DS1996 employs three address registers, called TA1, TA2 and E/S

(Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will be

written or from which data will be sent to the master upon a Read command. Register E/S acts like a byte

counter and Transfer Status register. It is used to verify data integrity with Write commands. Therefore,

the master only has read access to this register. The lower 5 bits of the E/S register indicate the address of

the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the E/S

integer multiple of 8. Bit 6, OF or ”Overflow,” is set if more bits are sent by the master than can be stored

in the scratchpad. Note that the lowest 5 bits of the target address also determine the address within the

scratchpad, where intermediate storage of data will begin. This address is called byte offset. If the target

address for a Write command is 13CH for example, then the scratchpad will store incoming data

beginning at the byte offset 1CH and will be full after only 4 bytes. The corresponding ending offset in

this example is 1FH. For best economy of speed and efficiency, the target address for writing should

point to the beginning of a new page, i.e., the byte offset will be 0. Thus the full 32-byte capacity of the

scratchpad is available, resulting also in the ending offset of 1FH. However, it is possible to write one or

several contiguous bytes somewhere within a page. The ending offset together with the Partial and

Overflow Flag is mainly a means to support the master checking the data integrity after a Write

command. The highest valued bit of the E/S register, called AA or Authorization Accepted, acts as a flag

to indicate that the data stored in the scratchpad has already been copied to the target memory address.

Writing data to the scratchpad clears this flag.

WRITING WITH VERIFICATION

To write data to the DS1996, the scratchpad has to be used as intermediate storage. First the master issues

the Write Scratchpad command to specify the desired target address, followed by the data to be written to

the scratchpad. In the next step, the master sends the Read Scratchpad command to read the scratchpad

and to verify data integrity. As preamble to the scratchpad data, the DS1996 sends the requested target

address TA1 and TA2 and the contents of the E/S register. If one of the flags OF or PF is set, data did not

arrive correctly in the scratchpad. The master does not need to continue reading; it can start a new trial to

write data to the scratchpad. Similarly, a set AA flag indicates that the Write command was not

recognized by the iButton. If everything went correctly, all three flags are cleared and the ending offset

indicates the address of the last byte written to the scratchpad. Now the master can continue verifying

every data bit. After the master has verified the data, it has to send the Copy Scratchpad command. This

command must be followed exactly by the data of the three address registers TA1, TA2 and E/S as the

master has read them verifying the scratchpad. As soon as the iButton has received these bytes, it will

copy the data to the requested location beginning at the target address.

MEMORY FUNCTION COMMANDS

The “Memory Function Flow Chart” (Figure 7) describes the protocols necessary for accessing the

memory. An example follows the flowchart. The communication between master and DS1996 takes place

either at regular speed (default, OD=0) or at Overdrive Speed (OD=1). If not explicitly set into the

Overdrive Mode the DS1996 assumes regular speed.

5 of 19

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