10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
Data Sheet
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
61.5 dBFS at 9.7 MHz input
61.0 dBFS at 200 MHz input
SFDR
75 dBc at 9.7 MHz input
73 dBc at 200 MHz input
Low power
45 mW at 20 MSPS
76 mW at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.10 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data alignment
RBIAS
VCM
PROGRAMMING DATA
VIN+
VIN–
ADC
CORE
AVDD
GND
SDIO SCLK CSB
AD9609
FUNCTIONAL BLOCK DIAGRAM
DRVDD
SPI
CMOS
OUTPUT BUFFER
OR
D9 (MSB)
D0 (LSB)
DCO
VREF
SENSE
REF
SELECT
DIVIDE
BY
1 TO 8
DCS
AD9609
MODE
CONTROLS
08541-001
CLK+ CLK–
PDWN
DFS
MODE
Figure 1.
PRODUCT HIGHLIGHTS
1.
The
AD9609
operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
The sample-and-hold circuit maintains excellent performance
for input frequencies up to 200 MHz and is designed for low
cost, low power, and ease of use.
A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO and data output
(D9 to D0) timing and offset adjustments, and voltage
reference modes.
The
AD9609
is packaged in a 32-lead RoHS compliant
LFCSP that is pin compatible with the
AD9629
12-bit ADC
and the
AD9649
14-bit ADC, enabling a simple migration
path between 10-bit and 14-bit converters sampling from
20 MSPS to 80 MSPS.
2.
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
PET/SPECT imaging
3.
4.
Rev. B
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AD9609
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings ............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 11
AD9609-80 .................................................................................. 11
AD9609-65 .................................................................................. 13
AD9609-40 .................................................................................. 14
AD9609-20 .................................................................................. 15
Equivalent Circuits ......................................................................... 16
Theory of Operation ...................................................................... 17
Analog Input Considerations.................................................... 17
Data Sheet
Voltage Reference ....................................................................... 19
Clock Input Considerations ...................................................... 20
Power Dissipation and Standby Mode .................................... 22
Digital Outputs ........................................................................... 22
Timing.......................................................................................... 23
Built-In Self-Test (BIST) and Output Test .................................. 24
Built-In Self-Test (BIST) ............................................................ 24
Output Test Modes ..................................................................... 24
Serial Port Interface (SPI) .............................................................. 25
Configuration Using the SPI ..................................................... 25
Hardware Interface ..................................................................... 26
Configuration Without the SPI ................................................ 26
SPI Accessible Features .............................................................. 26
Memory Map .................................................................................. 27
Reading the Memory Map Register Table............................... 27
Open Locations .......................................................................... 27
Default Values ............................................................................. 27
Memory Map Register Table ..................................................... 28
Memory Map Register Descriptions ........................................ 30
Applications Information .............................................................. 31
Design Guidelines ...................................................................... 31
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
2/2017—Rev. A to Rev. B
Added Endnote 1, Table 17 ........................................................... 28
Changes to Power and Ground Recommendations Section ..... 31
Added Soft Reset Section............................................................... 31
6/2015—Rev. 0 to Rev. A
Change to Product Highlights Section .......................................... 1
Changes to Figure 3 and Table 8 ................................................... 10
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
10/2009—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
GENERAL DESCRIPTION
The
AD9609
is a monolithic, single channel 1.8 V supply, 10-bit,
20/40/65/80 MSPS analog-to-digital converter (ADC). It features
a high performance sample-and-hold circuit and on-chip voltage
reference.
The product uses multistage differential pipeline architecture
with output error correction logic to provide 10-bit accuracy at
80 MSPS data rates and to guarantee no missing codes over the
full operating temperature range.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as programmable clock and data
alignment and programmable digital test pattern generation. The
available digital test patterns include built-in deterministic and
pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
AD9609
A differential clock input with selectable internal 1 to 8 divide ratio
controls all internal conversion cycles. An optional duty cycle
stabilizer (DCS) compensates for wide variations in the clock duty
cycle while maintaining excellent overall ADC performance.
The digital output data is presented in offset binary, gray code, or
twos complement format. A data output clock (DCO) is provided
to ensure proper latch timing with receiving logic. Both 1.8 V and
3.3 V CMOS levels are supported.
The
AD9609
is available in a 32-lead RoHS-compliant LFCSP
and is specified over the industrial temperature range (−40°C
to +85°C).
Rev. B | Page 3 of 32
AD9609
SPECIFICATIONS
DC SPECIFICATIONS
Data Sheet
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Integral Nonlinearity (INL)
2
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation Error at 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance
3
Input Common-Mode Voltage
Input Common-Mode Range
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD
2
IDRVDD
2
(1.8 V)
IDRVDD
2
(3.3 V)
POWER CONSUMPTION
DC Input
Sine Wave Input
2
(DRVDD = 1.8 V)
Sine Wave Input
2
(DRVDD = 3.3 V)
Standby Power
4
Power-Down Power
1
2
Temp
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
25°C
Full
Full
Full
Full
Full
AD9609-20/AD9609-40
Min
Typ
Max
10
Guaranteed
+0.05
+0.55
−1.5
±0.15/±0.25
±0.05/±0.08
±0.35
±0.15
±2
0.984
0.996
2
0.06
2
6
0.9
0.5
7.5
1.3
1.008
AD9609-65
Min
Typ
Max
10
Guaranteed
−0.45 +0.05 +0.55
−1.5
±0.25
±0.15
±0.45
±0.15
±2
0.984
0.996
2
0.08
2
6
0.9
0.5
7.5
1.3
1.008
AD9609-80
Min
Typ
Max
10
Guaranteed
−0.45 +0.05 +0.55
−1.5
±0.25
±0.07
±0.45
±0.15
±2
0.984
0.996
2
0.08
2
6
0.9
0.5
7.5
1.3
1.008
Unit
Bits
−0.45
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
V
mV
LSB rms
V p-p
pF
V
V
kΩ
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.7
1.7
1.8
1.9
3.6
27.0/32.0
1.7
1.7
1.8
1.9
3.6
39.5
1.7
1.7
1.8
1.9
3.6
45
V
V
mA
mA
mA
mW
mW
mW
mW
mW
24.9/29.7
1.4/2.2
2.5/4.1
45.2/54.7
46.3/57.4
53.1/67.0
34
0.5
37.1
3.6
6.6
67.7
73.3
88.6
34
0.5
41.8
4.3
7.9
76.3
83.0
89.5
34
0.5
52.0/61.0
78.0
92
Measured with 1.0 V external reference.
Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4
Standby power is measured with a dc input and the CLK active.
Rev. B | Page 4 of 32
Data Sheet
AC SPECIFICATIONS
AD9609
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 2.
Parameter
1
SIGNAL-TO-NOISE RATIO (SNR)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
f
IN
= 200 MHz
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
f
IN
= 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
f
IN
= 200 MHz
WORST SECOND OR THIRD HARMONIC
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
f
IN
= 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
f
IN
= 200 MHz
WORST OTHER (HARMONIC OR SPUR)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
f
IN
= 200 MHz
TWO-TONE SFDR
f
IN
= 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS)
ANALOG INPUT BANDWIDTH
1
Temp
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
AD9609-20/AD9609-40
Min
Typ
Max
61.7
61.7
61.2
61.6
AD9609-65
Min Typ
Max
61.5
61.5
61.0
61.5
AD9609-80
Min Typ
Max
61.5
61.5
61.5
61.0
61.0
61.4
61.4
61.4
60.5
60
9.9
9.9
9.9
9.6
−78
−80
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MHz
61.0
61.6
61.5
60.7/60.9
61.5
60.5
61.4
60
9.9
9.9
9.9
9.9
9.9
9.9
9.6
−78
−80
−67
−82
−78
−73
78
80.5
67
78
65.5
75
68
73
−82
−82
−74
−82
−80
−80
78
700
−80
−80
−72
75
75
−65.5
61.4
61.3
−81
−80
−78
−68
−73
75
75
75
73
−80
−80
−80
−73
−80
78
700
700
See the
AN-835 Application Note,
Understanding High Speed ADC Testing and Evaluation,
for a complete set of definitions.
Rev. B | Page 5 of 32
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