Data Sheet
FEATURES
3.1 nV/√Hz, 1 mA, 180 MHz,
Rail-to-Rail Input/Output Amplifiers
ADA4807-1/ADA4807-2/ADA4807-4
PIN CONNECTION DIAGRAMS
V
OUT 1
–V
S 2
+IN
3
6
Low input noise
3.1 nV/√Hz at f = 100 kHz with 29 Hz 1/f corner
0.7 pA/√Hz at f = 100 kHz with 2 kHz 1/f corner
High speed performance with dc precision
180 MHz, −3 dB bandwidth (G = +1, V
OUT
= 20 mV p-p)
225 V/μs slew rate for 5 V step (rise)
47 ns settling time to 0.1% for 4 V step
±125 μV and 3.7 μV/°C maximum input offset voltage and drift
100 nA and 250 pA/°C maximum input offset current and drift
Low distortion (HD2/HD3), V
S
= ±5 V, V
OUT
= 2 V p-p
−141 dBc/−144 dBc at 1 kHz
−112 dBc/−115 dBc at 100 kHz
−95 dBc/−79 dBc at 1 MHz
Low power operation
1.0 mA quiescent supply current per amplifier at ±5 V
Dynamic power scaling
Fully specified at +3 V, +5 V, and ±5 V supplies
Rail-to-rail inputs and outputs
+V
S
DISABLE
–IN
12611-001
5
4
Figure 1. 6-Lead SC70 and 6-Lead SOT-23 Pin Configuration (ADA4807-1)
V
OUT1 1
–IN1
2
+IN1
3
–V
S 4
8
7
6
5
+V
S
V
OUT2
+IN2
12611-058
–IN2
Figure 2. 8-Lead MSOP Pin Configuration (ADA4807-2)
V
OUT1
–IN1
+IN1
–V
S
DISABLE1
1
2
3
4
5
10
9
8
7
6
+V
S
V
OUT2
–IN2
+IN2
DISABLE2
Figure 3. 10-Lead LFCSP Pin Configuration (ADA4807-2)
V
OUT1 1
–IN1
2
+IN1
3
+V
S
4
+IN2
5
–IN2
6
V
OUT2 7
14
V
OUT4
13
–IN4
12
+IN4
APPLICATIONS
High resolution analog-to-digital converter (ADC) drivers
Portable and battery-powered instruments and systems
High component density data acquisition systems
Audio signal conditioning
Active filters
ADA4807-4
11
–V
S
10
+IN3
9
8
–IN3
V
OUT3
12611-104
Figure 4. 14-Lead TSSOP Pin Configuration (ADA4807-4)
GENERAL DESCRIPTION
The
ADA4807-1
(single),
ADA4807-2
(dual), and
ADA4807-4
(quad) are low noise, rail-to-rail input and output, voltage
feedback amplifiers. These amplifiers combine low power, low
noise, high speed, and dc precision to provide an attractive
solution for a wide range of applications from high resolution
data acquisition instrumentation to high performance battery-
powered and high component density systems where power
consumption is of key importance.
With only 1.0 mA of supply current per amplifier, the
ADA4807-1/
ADA4807-2/ADA4807-4
feature the lowest input voltage noise
among high speed, rail-to-rail input/output amplifiers in the
industry and offer a wide bandwidth, high slew rate, fast settling
time, and excellent distortion performance. Additionally, these
amplifiers offer very low input offset voltage and drift performance,
making them ideal for driving multiplexed and high throughput
precision 16-/18-bit successive approximation registers (SARs)
and 24-bit
-
ADCs.
Rev. B
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Trademarks and registered trademarks are the property of their respective owners.
These amplifiers are fully specified at +3 V, +5 V, and ±5 V supplies
and can operate over the industrial −40°C to +125°C
temperature range.
The
ADA4807-1
is available in 6-lead SOT-23 and space-saving
6-lead SC70 packages. The
ADA4807-2
is available in an 8-lead
MSOP and a compact, 3 mm × 3 mm, 10-lead LFCSP. The
ADA4807-4
is available in a 14-lead TSSOP package.
Table 1. Other Rail-to-Rail Amplifiers
Bandwidth
(MHz)
80
190
125
Slew
Rate
(V/μs)
35
90
62
Voltage
Noise
(nV/√Hz)
15
4.3
16.5
Max.
V
OS
(mV)
±1.5
0.8
5
Device
AD8031/AD8032
AD8027/AD8028
AD8029/AD8030/
AD8040
12611-059
ADA4807-1/ADA4807-2/ADA4807-4
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Connection Diagrams ............................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
±5 V Supply ................................................................................... 3
5 V Supply...................................................................................... 5
3 V Supply...................................................................................... 7
Absolute Maximum Ratings............................................................ 9
Maximum Power Dissipation ..................................................... 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 13
Frequency Response................................................................... 13
Frequency and Supply Current ................................................. 15
DC and Input Common-Mode Performance ......................... 16
Data Sheet
Slew, Transient, Settling Time, and Crosstalk............................. 18
Distortion and Noise.................................................................. 20
Output Characteristics............................................................... 22
Overdrive Recovery and Turn On/Turn Off Times .............. 23
Theory of Operation ...................................................................... 24
Disable Circuitry ........................................................................ 25
Input Protection ......................................................................... 25
Noise Considerations ................................................................. 25
Applications Information .............................................................. 26
Capacitive Load Drive ............................................................... 26
Low Noise FET Operational Amplifier ................................... 26
Power Mode ADC Driver ......................................................... 27
ADC Driving............................................................................... 28
ADC Driving with Dynamic Power Scaling ........................... 29
Layout, Grounding, and Bypassing .......................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 33
REVISION HISTORY
9/15—Rev. A to Rev. B
Added ADA4807-4 ............................................................. Universal
Changes to Features Section, General Description Section, and
Table 1 .......................................................................................................... 1
Added Figure 4, Renumbered Sequentially .................................. 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Changes to Table 4 ............................................................................ 7
Deleted Figure 6, Renumbered Sequentially............................... 10
Changes to Figure 6 ........................................................................ 10
Added Figure 9 and Table 9, Renumbered Sequentially ........... 12
Changes to Figure 20 ...................................................................... 14
Added Figure 21.............................................................................. 14
Added Figure 31 and Figure 32..................................................... 16
Added Figure 35.............................................................................. 17
Changes to Figure 39 ...................................................................... 18
Added Figure 42.............................................................................. 19
Deleted Figure 50, Figure 51, Figure 53, and Figure 54 ............. 19
Added Figure 46.............................................................................. 20
Added Figure 49 and Figure 51..................................................... 21
Added Figure 59 and Figure 61..................................................... 23
Changes to DISABLE Circuitry Section ...................................... 25
Added Low Noise FET Operational Amplifier Section............. 26
Added Figure 70, Figure 71, Figure 72, and Power Mode ADC
Driver Section ................................................................................. 27
Added ADC Driving Section and Figure 73 through Figure 77..... 28
Added ADC Driving with Dynamic Power Scaling Section,
Figure 78, Figure 79, and Figure 80 .............................................. 29
Added Figure 58 ............................................................................. 33
Changes to Ordering Guide .......................................................... 33
4/15—Rev. 0 to Rev. A
Added ADA4807-2 ............................................................. Universal
Changes to Features Section, General Description
Section, and Pin Connection Diagrams Heading .........................1
Added Figure 2 and Figure 3; Renumbered Sequentially ............1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................5
Changes to Table 3.............................................................................7
Changes to Table 6 and Figure 4 ......................................................9
Added Figure 7, Figure 8, and Table 8; Renumbered Sequentially ....11
Reorganized Layout, Typical Performance Characteristics
Section.............................................................................................. 12
Added Figure 36 ............................................................................. 16
Changes to Figure 37 Caption, Figure 38 Caption, Figure 39
Caption, and Figure 40 Caption ................................................... 17
Changes to Figure 44 and Figure 47............................................. 18
Change to Theory of Operation Section ..................................... 20
Changes to DISABLE Circuitry Section, Table 9, and Noise
Considerations Section .................................................................. 21
Added Figure 65 and Figure 66 .................................................... 23
Changes to Ordering Guide .......................................................... 25
12/14—Revision 0: Initial Version
Rev. B | Page 2 of 33
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