www.fairchildsemi.com
ML2003, ML2004
Logarithmic Gain/Attenuator
Features
Low noise: 0 dBrnc max with +24dB gain
Low harmonic distortion: -60dB max
Gain range: –24 to +24dB
Resolution: 0.1dB steps
Flat frequency response:
±0.05dB from .3–4 kHz
±0.10dB from .1-20 kHz
• Low supply current 4mA max from ±5V supplies
• TTL/CMOS compatible digital interface
• ML2003 has pin selectable serial or parallel interface;
ML2004 serial interface only
•
•
•
•
•
General Description
The ML2003 and ML2004 are digitally controlled logarith-
mic gain/attenuators with a range of –24 to +24 dB in 0.1 dB
steps.
The gain settings are selected by a 9-bit digital word.
The ML2003 digital interface is either parallel or serial.
The ML2004 is packaged in a 14-pin DIP with a serial
interface only.
Absolute gain accuracy is 0.05dB max over supply tolerance
of ±10% and temperature range.
These CMOS logarithmic gain/attenuators are designed for a
wide variety of applications in telecom, audio, sonar, or gen-
eral purpose function generation. One specific intended
application is analog telephone lines.
Block Diagram
V
CC
P
DN
A GND
V
SS
GND
Pin Connections
ML2003
18-PIN DIP
C3
+
FINE
–
+
BUFFER
–
V
OUT
(LATI)C2
(SID)C1
(LATO)C0
P
DN
F3
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
TOP VIEW
ATTEN/GAIN
V
CC
V
OUT
V
SS
A GND
V
IN
NC
F0 (SOD)
SER/PAR
C0 (LATO)
NC
P
DN
F3
F2 (SCK)
4
5
6
7
8
9 10 11 12 13
F1
GND
SER/PAR
V
IN
+
COURSE
–
ML2003
20-Pin PCC
C1 (SID)
C2 (LATI)
C3
ATTEN/GAIN
RESISTORS/
SWITCHES
16
RESISTORS/
SWITCHES
16
(SCK)F2
F1
GND
3 2 1 20 19
18
17
16
15
14
V
OUT
V
SS
A GND
NC
NC
DECODER/MODE SELECTOR
C0
C1
C2
C2
(LATI)
C1
(SID)
F0
F2
9
SER/PAR
ML2004
14-PIN DIP
C0
(LATO)
F0
(SOD)
LATI
SID
LATO
1
2
3
4
5
6
7
14
13
12
11
10
9
8
TOP VIEW
V
CC
V
OUT
V
SS
A GND
V
IN
NC
SOD
9-BIT LATCH &
SHIFT REGISTER
TOP VIEW
ATTEN/
GAIN
C3
F1
F3
F2
(SCK)
P
DN
SCK
NOTE: SERIAL MODE FUNCTIONS INDICATED BY PARENTHESES.
NC
GND
REV. 1.1.1 3/19/01
F0 (SOD)
V
IN
V
CC
ML2003, ML2004
PRODUCT SPECIFICATION
Pin Description
Name
C3
(LATI) C2
(SID) C1
(LATO) C0
P
DN
F3
(SCK) F2
Function
In serial mode, pin is unused. In parallel mode, coarse gain select bit. Pin has internal pulldown
resistor to GND.
In serial mode, input latch clock which loads the data from the shift register into the latch.
In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND.
In serial mode, serial data input that contains serial 9 bit data word which controls the gain
setting. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND.
In serial mode, output latch clock which loads the 9 bit data word back into the shift register from
the latch. In parallel mode, coarse gain select bit. Pin has internal pulldown resistor to GND.
Powerdown input
. When P
DN
= 1, device is in powerdown mode. When P
DN
= 0, device is in
normal operation. Pin has internal pulldown resistor to GND.
In serial mode, pin is unused. In parallel mode, fine gain select bit. Pin has internal pulldown
resistor to GND.
In serial mode, shift register clock which shifts the serial data on SID into the shift register on
rising edges and out on SOD on falling edges. In parallel mode, fine gain select bit. Pin has
internal pulldown resistor to GND.
In serial mode, pin is unused. In parallel mode, fine gain select bit. Pin has internal pulldown
resistor to GND.
Digital ground
. 0 volts. All digital inputs and outputs are referenced to this ground.
Serial or parallel select input. When SER/PAR = 1, device is in serial mode.
When SER/PAR = 0, device is in parallel mode. Pin has internal pullup resistor to V
CC
.
In serial mode, serial output data which is the output of the shift register. In parallel mode, fine
gain select bit. Pin has internal pulldown resistor to GND.
Analog input
.
Analog ground
. 0 volts. Analog input and output are referenced to this ground.
Negative supply
. –5 volts ±10%.
Analog output
.
Positive supply
. +5 volts ±10%.
In serial mode, pin is unused. In parallel mode, attenuation/gain select bit. Pin has internal
pulldown resistor to GND.
F1
GND
SER/PAR
(SOD) F0
V
IN
AGND
V
SS
V
OUT
V
CC
ATTEN/GAIN
Absolute Maximum Ratings
1
Parameter
Supply Voltage
V
CC
V
SS
AGND with respect to GND
Analog Input and Output
Digital Input and Outputs
Input Current Per Pin
Power Dissipation
Storage Temperature Range
Lead Temeperature (Soldering, 10 sec)
-65
V
SS
–0.3V
GND –0.3
Min.
Max.
+6.5
-6.5
±0.5
V
CC
+0.3
V
CC
+0.3
±25
750
+150
300
Units
V
V
V
V
V
mA
mW
°C
°C
2
REV. 1.1.1 3/19/01
PRODUCT SPECIFICATION
ML2003, ML2004
Operating Conditions
Parameter
Temperature Range
2
ML2003CX, ML2004CX
ML2003IX, ML2004IX
Supply Voltage
V
CC
V
SS
Min.
0
-40
4
-4
Max.
70
85
6
-6
Units
°C
°C
V
V
Electrical Characteristics
Unless otherwise specified T
A
= T
MIN
to T
MAX
, V
CC
= 5V ± 10%, V
SS
= -5V ±10%, Data Word: ATTEN/GAIN = 1,
Other Bits = 0(0dB Ideal Gain), C
L
= 100pF, R
L
= 600
Ω
, SCK = LATI = LATO = 0, dBm measurements use 600
Ω
as
reference load, digital timing measured at 1.4 V, C
L
= 100pF or SOD.
Symbol
Analog
AG
RG
Absolute gain
accuracy
Relative gain
accuracy
4
4
V
IN
=8dBm, 1 kHz
100000001
000000000
000000001
All other gain settings
All values referenced to 100000000 gain
when ATTEN/GAIN = 1, V
IN
=8dBm when
ATTEN//GAIN =0
V
IN
=(8dBm – Ideal Gain) in dB
300-4000 Hz
100-20,000 Hz
Relative to 1 kHz
V
IN
= 0, +24dB gain
V
IN
= 0, +24dB gain, C msg. Weighted
V
IN
= 0, +24dB gain, 1kHz
V
IN
= 8dBm gain, 1kHz Measure 2nd,
3rd harmonic relative to fundamental
V
IN
= 8dBm, 1 kHz
C msg. weighted
200mVp-p, 1 kHz sine, V
IN
= 0
on V
CC
on V
SS
1
±3.0
±3.0
0.8
2.0
I
OL
= 2mA
0.4
+60
-6
450
-0.05
-0.05
-0.05
-0.05
-0.1
+0.05
+0.05
+0.05
+0.05
+0.1
dB
dB
dB
dB
dB
Parameter
Notes
Conditions
Min. Typ.
3
Max.
Units
FR
Frequency response
4
-0.05
-0.1
+0.05
+0.1
±100
dB
dB
mV
VOS
ICN
HD
SD
PSRR
Output Offset Voltage
Idle Channel Noise
Harmonic Distortion
Signal to Distortion
Power Supply
Rejection
Input impedance, V
IN
Input Voltage Range
Output Voltage Swing
Digital Input Low
Voltage
Digital Input High
Voltage
Digital Output Low
Voltage
4
4
5
4
4
4
0
dBrnc
900 nv/
√
Hz
-60
dB
dB
-60
-60
-40
-40
dB
dB
Meg
V
V
V
V
V
Z
IN
V
INR
V
OSW
V
IL
V
IH
V
OL
4
4
4
4
4
4
Digital and DC
REV. 1.1.1 3/19/01
3
ML2003, ML2004
PRODUCT SPECIFICATION
Electrical Characteristics
(continued)
Unless otherwise specified T
A
= T
MIN
to T
MAX
, V
CC
= 5V ± 10%, V
SS
= -5V ±10%, Data Word: ATTEN/GAIN = 1,
Other Bits = 0(0dB Ideal Gain), C
L
= 100pF, R
L
= 600Ω, SCK = LATI = LATO = 0, dBm measurements use 600Ω as
reference load, digital timing measured at 1.4 V, C
L
= 100pF or SOD.
Symbol
V
OH
I
NS
I
ND
Parameter
Digital Output High
Voltage
Input Current, SER/
PAR
Input Current,
All Digital Inputs
Except SER/PER
V
CC
Supply Current
V
SS
Supply Current
V
CC
Supply Current,
Powerdown Mode
V
SS
Supply Current
Powerdown Mode
V
OUT
Settling Time
Notes
4
4
4
I
OH
= -1mA
V
IH
= GND
V
IH
= V
CC
Conditions
Min. Typ.
3
Max.
4.0
-5
5
-100
100
Units
V
µA
µA
I
CC
I
SS
I
CCP
I
SSP
4
4
4
4
No output load, V
IL
= GND,
V
IH
= V
CC
, V
IN
= 0
No output load, V
IL
= GND,
V
IH
= V
CC
, V
IN
= 0
No output load, V
IL
= GND,
V
IH
= V
CC
No output load, V
IL
= GND,
V
IH
= V
CC
V
IN
= 0.185V. Change gain from –24 to
+24dB. Measure from LATI rising edge to
when V
OUT
settles to within 0.05dB of final
value.
Gain = +24dB. V
IN
= -0.185 to +0.185V
step. Measure when V
OUT
settles to within
0.05dB of final value.
250
50
50
0
50
50
50
50
0
4
-4
0.5
-0.1
mA
mA
mA
mA
AC Characteristics
t
SET
4
20
µs
t
STEP
V
OUT
Step Response
4
20
µs
t
SCK
t
S
t
H
t
D
t
IPW
t
OPW
SCK On/Off Period
SID Data Setup Time
SID Data Hold Time
SOD Data Delay
LATI Pulse Width
LATO Pulse Width
4
4
4
4
4
4
4
5
4
ns
ns
ns
125
ns
ns
ns
ns
ns
125
ns
t
IS
, t
OS
LATI, LATO Setup
Time
t
IH
,
t
OH
t
PLD
LATI, LATO Hold
Time
SOD Parallel Load
Delay
Notes:
1. Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless
otherwise specified are measured with respect to ground.
2. 0°C to +70°C and –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed
by 100% testing, sampling, or by correlation with worst-case test conditions.
3. Typicals are parametric norm at 25°C.
4. Parameter guaranteed and 100% production tested.
5. Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
4
REV. 1.1.1 3/19/01
PRODUCT SPECIFICATION
ML2003, ML2004
Timing Diagram
t
SCK
SCK
t
S
SID
t
D
SOD
t
H
t
SCK
SCK
t
IS
LATI
t
IPW
LATO
t
PLD
SOD
t
OPW
t
IH
t
OS
t
OH
TIMING PARAMETERS ARE REFERENCED TO THE 1.4 VOLT MIDPOINT.
Figure 1. Serial Mode Timing Diagram
Typical Performance Curves
0
-0.5
-0.10
GAIN = +24dB
AMPLITUDE (dB)
GAIN = +18dB
-0.20
GAIN = +12dB
-0.25
-0.30
-0.35
-0.40
-0.45
-0.50
100
1K
10K
FREQUENCY (Hz)
100K
GAIN = +0, -24dB
AMPLITUDE (dB)
-0.15
-0.15
-0.20
-0.25
-0.30
-0.35
-0.40
-0.45
-0.50
100
1K
10K
FREQUENCY (Hz)
100K
GAIN = 0dB
GAIN = –24dB
ATTEN: V
IN
= 0.5V
RMS
GAIN: V
IN
= 0.5V
RMS
/GAIN SETTING
0
-0.5
-0.10
ATTEN: V
IN
= 2V
RMS
GAIN: V
IN
= 2V
RMS
/GAIN SETTING
GAIN = +24dB
Figure 2. Amplitude vs Frequency (V
IN
/V
OUT
= .5V
RMS
)
Figure 3. Amplitude vs Frequency (V
IN
/V
OUT
= 2V
RMS
)
REV. 1.1.1 3/19/01
5
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