Data Sheet
FEATURES
Supports input data rates up to 1.125 GSPS
Proprietary low spurious and distortion design
Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc
at 180 MHz IF
SFDR = 72 dBc at 150 MHz IF, −6 dBFS
Flexible 4-lane JESD204B interface
Multiple chip synchronization
Fixed latency
Data generator latency compensation
Selectable 1×, 2×, 4×, and 8× interpolation filter
Low power architecture
Input signal power detection
Emergency stop for downstream analog circuitry protection
Transmit enable function allows extra power saving
High performance, low noise, phase-locked loop (PLL) clock
multiplier
Digital inverse sinc filter and programmable finite impulse
response (FIR) filter
Low power: 1223 mW at 1.5 GSPS, 1406 mW at 2.0 GSPS, full
operating conditions
56-lead LFCSP with exposed pad
Dual, 16-Bit, 2.25 GSPS, TxDAC+
Digital-to-Analog Converter
AD9152
GENERAL DESCRIPTION
The
AD9152
is a dual, 16-bit, high dynamic range digital-to-
analog converter (DAC) that provides a maximum sample rate of
2.25 GSPS, permitting a multicarrier generation up to the Nyquist
frequency. The DAC outputs are optimized to interface seam-
lessly with the
ADRF6720
analog quadrature modulator (AQM)
from Analog Devices, Inc. An optional 3-wire or 4-wire serial
port interface (SPI) provides for programming/readback of
many internal parameters. The full-scale output current can be
programmed over a range of 4 mA to 20 mA. The
AD9152
is
available in a 56-lead LFCSP. The
AD9152
is a member of the
TxDAC+® family.
PRODUCT HIGHLIGHTS
1.
2.
Ultrawide signal bandwidth enables emerging wideband
and multiband wireless applications.
Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
JESD204B Subclass 1 support simplifies multichip
synchronization in software and hardware design.
Fewer pins for data interface width with the serializer/
deserializer (SERDES) JESD204B four-lane interface.
Programmable transmit enable function allows easy design
balance between power consumption and wake-up time.
Small package size with an 8 mm × 8 mm footprint.
3.
4.
5.
6.
APPLICATIONS
Wireless communications
Multicarrier LTE and GSM base stations
Wideband repeaters
Software defined radios
Wideband communications
Point to point microwave radios
LMDS/MMDS
Transmit diversity, multiple input/multiple output (MIMO)
Instrumentation
Automated test equipment
FUNCTIONAL BLOCK DIAGRAM
CTRL
QUAD MOD
ADRF6720
LPF
DUAL
DAC
DAC
RF
OUTPUT
AMP
AMP
0/90° PHASE
SHIFTER
DAC
JESD204B
SYNC
SYSREF
VGA
AD9152
DAC
SPI
12994-001
LO_IN
MOD_SPI
Figure 1.
Rev. B
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
AD9152
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Detailed Functional Block Diagram .............................................. 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
Digital Specifications ................................................................... 6
Maximum DAC Update Rate Speed Specifications by
Supply ............................................................................................. 7
JESD204B Serial Interface Speed Specifications ...................... 7
SYSREF± to DAC Clock Timing Specifications ....................... 8
Digital Input Data Timing Specifications ................................. 8
Latency Variation Specifications ................................................ 9
JESD204B Interface Electrical Specifications ........................... 9
AC Specifications........................................................................ 10
Absolute Maximum Ratings .......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution ................................................................................ 11
Pin Configuration and Function Descriptions ........................... 12
Terminology .................................................................................... 14
Typical Performance Characteristics ........................................... 15
Theory of Operation ...................................................................... 20
Serial Port Operation ..................................................................... 21
Data Format ................................................................................ 21
Serial Port Pin Descriptions ...................................................... 21
Serial Port Options ..................................................................... 21
Chip Information ............................................................................ 23
Device Setup Guide ........................................................................ 24
Overview...................................................................................... 24
Step 1: Start Up the DAC ........................................................... 24
Step 2: Digital Datapath ............................................................. 25
Step 3: Transport Layer .............................................................. 25
Step 4: Physical Layer ................................................................. 26
Step 5: Data Link Layer .............................................................. 26
Step 6: Optional Error Monitoring .......................................... 26
Step 7: Optional Features ........................................................... 26
DAC PLL Setup ........................................................................... 27
Data Sheet
Interpolation ............................................................................... 27
JESD204B Setup ......................................................................... 27
SERDES Clocks Setup ................................................................ 28
Equalization Mode Setup .......................................................... 28
Link Latency Setup ..................................................................... 28
Crossbar Setup ............................................................................ 30
JESD204B Serial Data Interface .................................................... 31
JESD204B Overview .................................................................. 31
Physical Layer ............................................................................. 32
Data Link Layer .......................................................................... 35
Transport Layer .......................................................................... 43
JESD204B Test Modes ............................................................... 51
JESD204B Error Monitoring..................................................... 52
Digital Datapath ............................................................................. 54
Data Format ................................................................................ 54
Interpolation Filters ................................................................... 54
Digital Modulation ..................................................................... 55
NCO Alignment ......................................................................... 56
Inverse Sinc ................................................................................. 57
Programmable FIR Filter (PFIR) ............................................. 57
Digital Gain, Phase Adjust, DC Offset, and Coarse Group
Delay ............................................................................................ 57
Downstream Protection ............................................................ 59
Datapath PRBS ........................................................................... 61
DC Test Mode ............................................................................. 62
Interrupt Request Operation ........................................................ 63
Interrupt Service Routine .......................................................... 63
DAC Input Clock Configurations ................................................ 64
Driving the DACCLK± AND REFCLK± Inputs ................... 64
Condition Specific Register Writes .......................................... 64
Starting the PLL .......................................................................... 65
Analog Outputs............................................................................... 67
Transmit DAC Operation.......................................................... 67
Temperature Sensor ....................................................................... 68
Example Start-Up Sequence .......................................................... 69
Step 1: Start Up the DAC ........................................................... 69
Step 2: Digital Datapath ............................................................. 70
Step 3: Transport Layer .............................................................. 70
Step 4: Physical Layer ................................................................. 70
Step 5: Data Link Layer.............................................................. 70
Rev. B | Page 2 of 103
Data Sheet
Step 6: Optional Error Monitoring ...........................................70
Board Level Hardware Considerations ........................................71
Power Supply Recommendations .............................................71
JESD204B Serial Interface Inputs (SERDIN0± to
SERDIN3±) ...................................................................................71
Register Map and Descriptions .....................................................74
AD9152
Device Configuration Register Map ......................................... 74
Device Configuration Register Descriptions .......................... 79
Outline Dimensions ......................................................................103
Ordering Guide .........................................................................103
REVISION HISTORY
8/2017—Rev. A to Rev. B
Change to Output Compliance Range Parameter; Table 1 .......... 5
Updated Outline Dimensions ......................................................103
Changes to Ordering Guide .........................................................103
2/2017—Rev. 0 to Rev. A
Changes to Figure 2........................................................................... 4
Change to Device Revision Parameter, Table 14 .........................23
Changes to Step 1: Start Up the DAC Section and Table 16 ......24
Changes to Digital Datapath Section, Address 0x14, Table 17,
and Table 18 .....................................................................................26
Change to JESD204B Setup Section .............................................27
Changes to SERDES PLL Fixed Register Writes Section ...........33
Added Table 36; Renumbered Sequentially .................................33
Change to Register Block 0x47, Bit 4, Table 69 ...........................63
Deleted DAC PLL Fixed Register Writes Section, Figure 70, and
Figure 71; Renumbered Sequentially ............................................64
Changes to Temperature Tracking Section, Starting the PLL
Section, and Table 73 ......................................................................65
Changes to Table 76 and Table 77 .................................................69
Changes to Table 78 ........................................................................70
Changes to Table 85 ........................................................................74
Changes to Table 86 ........................................................................80
4/2015—Revision 0: Initial Version
Rev. B | Page 3 of 103
AD9152
DETAILED FUNCTIONAL BLOCK DIAGRAM
DIV
PLL
(40×)
DACCLK
Data Sheet
AD9152
I/Q
CLOCK DATA RECOVERY
AND CLOCK FORMATTER
SERDIN3±
HB1
HB2
HB3
FIFO
MODULUS DDS
MODE CONTROL
COARSE DDS
±(
f
DAC
/4), ±(
f
DAC
/8) × N
HB1
HB2
HB3
DOWNSTREAM PROTECTION
INV
SINC
PHASE
ADJUST
DC
OFFSET
COARSE GROUP
DELAY
NCO FINE
MODULATION
PFIR
DIGITAL
GAIN
[10:0]
I DAC
16-BIT
IOUT+
IOUT–
DACCLK
SERDIN0±
Q DAC
16-BIT
QOUT+
QOUT–
PDP
SYNCOUT+
SYNCOUT–
JESD204B ERRORS
SYNCHRONIZATION
LOGIC
SPI
TXEN
CLK_SEL
GAIN
GAIN
REF AND
BIAS
SYSREF
RCVR
CONFIG
REGISTERS
CLOCK DISTRIBUTION
AND
CONTROL LOGIC
PLL_CTRL
DACCLK
DAC
ALIGN
DETECT
I120
SYSREF+
SYSREF–
DACCLK+
DACCLK–
REFCLK+
REFCLK–
12994-002
CLK
RECIEVER
SERIAL I/O
PORT
POWER-ON
RESET
DAC
PLL
PLL_LOCK
DIV
(2, 4, 16, 32)
REF
RECIEVER
RESET
SDO
SDIO
SCLK
CS
TXEN
IRQ
Figure 2. Detailed Functional Block Diagram
Rev. B | Page 4 of 103
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AD9152
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, PLLVDD12 = 1.2 V,
SVDD12 = 1.2 V, SDVDD12 = 1.2 V, V
TT
= 1.2 V, T
A
= −40°C to +85°C, I
OUTFS
= 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Gain Error
I/Q Gain Mismatch
Full-Scale Output Current (I
OUTFS
)
Maximum Setting
Minimum Setting
Output Compliance Range
Output Resistance
Output Capacitance
Gain DAC Monotonicity
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
ANALOG SUPPLY VOLTAGES
AVDD33
PVDD12, CVDD12
SVDD12, PLLVDD12, V
TT
DIGITAL SUPPLY VOLTAGES
DVDD12, SDVDD12
SIOVDD33
IOVDD
POWER CONSUMPTION
Total Power
Test Conditions/Comments
Min
Typ
16
±5.0
±10.0
With internal reference
Based on a 4 kΩ external resistor between I120 and ground
19.1
3.8
2.3
20.22
4.04
15
3.0
Guaranteed
0.1
35
25
0.5
±5%
±5%
±2%
±5%
±2%
±5%
±2%
±5%
±5%
2× interpolation mode, f
DAC
= 1.5 GSPS, IF = 70 MHz, PLL
off, INVSINC on, digital gain on, NCO on, JESD204B
Mode 4, four SERDES lanes with 7.5 Gbps lane rate,
I
OUTFS
= 20 mA
3.13
1.14
1.274
1.14
1.274
1.14
1.274
3.13
1.71
3.3
1.2
1.3
1.2
1.3
1.2
1.3
3.3
1.8
1223
3.47
1.26
1.326
1.26
1.326
1.26
1.326
3.47
3.47
21.4
4.3
3.47
mA
mA
V
MΩ
pF
−5.5
−4.5
−1.3
+5.5
+4.5
Max
Unit
Bits
LSB
LSB
% FSR
% FSR
ppm/°C
ppm/°C
ppm/°C
V
V
V
V
V
V
V
V
V
V
mW
AVDD33
PVDD12
CVDD12
SDVDD12 and SVDD12
(Includes PLLVDD12 and V
TT
)
DVDD12
SIOVDD33 and IOVDD
OPERATING TEMPERATURE RANGE
87
11
179
328
246
5.7
+25
mA
mA
mA
mA
mA
mA
°C
−40
+85
Rev. B | Page 5 of 103
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