HV311DB2
Hotswap Controller
Introduction
The Supertex HV311DB2 demo board contains all necessay
circuitry to demonstrate the features of the HV311 hotswap
controller. Intended primarily as a negative hotswap
controller, the HV311 controls the negative supply path.
Included on board is a 100'F capacitor to provide a
capacitive load for testing. Additional capacitance (up to
2000'F) may be connected to the V
OUT
terminals, or the
100'F may be removed altogether
The board may be modified to meet custom requirements.
Instructions are provided on the next page for modifications.
Specifications
Input Voltage
Inrush Limit
Circuit Breaker Trip
Retry Interval
On Resistance
Undervoltage Trip
Overvoltage Trip
Power Good Signal
10V to 90V
1A ±20%
2A ±20%
12sec min
165m
6
max
35.0V on, 32.2V off
64.5V on, 70.0V off
Active Low
Board Layout and Connections
+
VIN
enable
-
Power Supply
or Load
V
IN
Connect the supply voltage to these terminals. Supply
voltage may range from 10 volts to 90 volts.
A high source impedance may cause oscillations when the
input voltage is near the undervoltage trip point. A high
source impedance results in a large voltage drop when
loaded, causing undervoltage lockout to kick in,
disconnecting the load. With the load removed, input
voltage rises, causing undervoltage to release and
reconnecting the load. The cycle repeats, resulting in
oscillations. Source impedance must be less than the
following to avoid oscillations:
HV311 shuts off, retrying 12s later. For this reason, DC load
at start-up should be less than 900mA. Note that DC start-
up load limitation decreases with added load capacitance.
Adding external load capacitance increases inrush limit time.
Since inrush time is internally limited to 100ms, a maximum
of 2000'F may be added
PWRGD
Connect to the power supply’s ENABLE input. Depending
on the power supply, it may be necessary to level-translate
this signal via opto-isolator or discrete circuit. Refer to the
HV301/311 data sheet for a description of PWRGD and
related application circuits.
PWRGD is an open-drain output. During start-up and
whenever V
IN
is lower than the undervoltage trip point or
greater than the overvoltage trip point, PWRGD is high
impedance. Once V
IN
is within the proper range and V
OUT
has stabilized, PWRGD is pulled down to V
IN–
.
R
SOURCE
<
V
OUT
3V
I
LOAD
Connect the power supply or other load to these terminals.
V
OUT+
is permanently connected to V
IN+
, it is V
OUT–
that is
switched.
Application of a DC load during start-up extends the time
inrush limiting is active. If this time exceeds 100ms, the
rev 1 10OCT01
1
HV311DB2
Hotswap Controller
Schematic
V
IN+
R
1
487k
UV
R
2
9.09k
R
3
9.09k
OV
RAMP
C
4
10nF
R
6
not used
V
IN–
R
SENSE
50m
V
EE
SENSE
GATE
C
4
100'F
C
5
not used
C
1
not used
V
DD
PWRGD
IC
1
R
7
not used
PWRGD
V
OUT+
HV311
C
2
not used
R
4
0
C
3
not used
R
5
not used
Q
1
IRFR120N
V
OUT–
Inrush Limit
As supplied, the inrush current limit is set at 1 amp. To set
inrush limit to another value, change current sense resistor
R
SENSE
according to the formula:
Circuit Breaker Transient Immunity
The HV311 has built-in transient immunity of 2–5's. To
increase transient immunity, an RC low-pass filter (R
4
C
2
)
may be placed on the SENSE input. (The demo board is
supplied with no filtering.)
Be aware that filtering the sense input will cause the inrush
current limit to overshoot at turn-on – the greater the filtering,
the greater the overshoot.
R
SENSE
=
50mV
I
INRUSH
The circuit breaker trip point (I
CB
) is 2 times the inrush limit.
For other ratios, refer to the ‘Programming Inrush & I
CB
’
section of the HV301/311 data sheet.
The power rating of R
SENSE
should be selected based on
maximum current during normal operation, which could be
just under the circuit breaker trip point.
Undervoltage/Overvoltage Lockout
Resistors R
1
, R
2
, and R
3
set the undervoltage and
overvoltage trip points. New trip points may be programmed
by changing the values of these resistors. Refer to the
HV301/311 data sheet for more information.
P
SENSE
=
I
CB
2
R
SENSE
Timing
Timing capacitor C
4
determines start-up delay, rise time, and
circuit breaker retry interval. Changing C
4
will alter these
timings. Refer to the HV301/311 datasheet for the equations
that relate these timings to the value of C
4
. For use in the
equations, the nominal gate threshold voltage (V
GS
) of the
supplied IRFR120N is 3V and transconductance is about 10
siemens.
Additional Components
The RC network (R
5
C
3
) across the gate-source of the
external FET provides control loop compensation which
prevents inrush current peaking.
A resistor at R
7
can be used to provide a passive pull-up for
the PWRGD signal.
A 10nF capacitor at C
1
may be needed for stability to limit
dV/dt if PWRGD experiences large voltage swings.
A 2.4M resistor in the R
6
location can be used to defeat the
circuit breaker auto-retry function.
rev 1 10OCT01
2
Microchip MCU
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