19-2252; Rev 0; 12/01
MAX9205 Evaluation Kit
General Description
The MAX9205 evaluation kit (EV kit) is a fully assembled
and tested circuit board that simplifies the evaluation of
the MAX9205 400Mbps, 10-bit serializer and the
MAX9206 400Mbps, 10-bit deserializer. The MAX9205
IC transforms 10-bit parallel LVCMOS/LVTTL data into a
serial high-speed bus low-voltage differential signaling
(BLVDS) data stream. The MAX9206 accepts serial
data from the MAX9205 and transforms it back to 10-bit-
wide LVCMOS/LVTTL parallel data.
The EV kit requires a single 3.3V supply and a refer-
ence clock input with a range of 16MHz to 40MHz to
operate. The 10-bit parallel input data is connected to a
24-pin header and the output data is sampled at a sep-
arate 24-pin header. The EV kit circuit can be modified
to isolate and evaluate the MAX9205 and MAX9206
independently. The MAX9205 and MAX9206 serializ-
er/deserializer pair can be replaced with the MAX9207
and MAX9208 serializer/deserializer pair that operates
at a higher maximum data-transfer speed of 600Mbps
with a clock input frequency of 40MHz to 60MHz.
o
3.3V Single Supply
o
10-Bit Parallel LVCMOS/LVTTL Interface
o
Allows Common-Mode Testing
o
Independent Evaluation of Serializer (MAX9205)
and Deserializer (MAX9206)
o
Allows Testing of Twisted-Pair Cable
o
Low-Voltage, Low-Power Operation
o
Fully Assembled and Tested
Features
Evaluates: MAX9205–MAX9208
Ordering Information
PART
MAX9205EVKIT
TEMP RANGE
0°C to +70°C
IC PACKAGE
28 SSOP
Component List
DESIGNATION
QTY
DESCRIPTION
10µF
±20%,
10V tantalum
capacitors (B)
AVX TAJB106M010 or
Kemet T494B106K010AS
0.001µF
±5%,
50V ceramic
capacitors (0603)
TDK C1608X7R1H102KT or
Murata GRM39X7R102J050AD
0.1µF
±10%,
16V ceramic
capacitors (0603)
TDK C1608X7R1C104KT or
Murata GRM39X7R104K016AD
5.0pF, 50V COG ceramic
capacitors (0603)
TDK C1608COG1H050CT
Murata GRM39COG050B050AD
2.2µF
±20%,
10V tantalum
capacitor (A)
AVX TAJA225M010R
DESIGNATION
QTY
DESCRIPTION
10pF, 50V COG ceramic
capacitors (0603)
TDK C1608COG1H100DT or
Murata GRM39COG100D050AD
2 x 12-pin headers
3-pin headers
2-pin headers
10kΩ
±5%
resistors (0603)
Not installed, resistor (0603)
49.9Ω
±1%
resistors (0603)
100Ω
±1%
resistor (0603)
Not installed, resistor (0805)
Not installed, resistor (1206)
499Ω
±1%
resistors (0603)
C1–C4
4
C27–C38
12
J1, J2
JU1, JU3–JU7
JU2, JU9,
JU10,
JU12–JU27
R1–R10, R97
R11–R20,
R79–R89,
R91–R95
R21–R39, R96
R40
R41–R50, R75
R51, R52
R53–R74, R77,
R78
2
6
19
11
0
20
1
0
0
24
C5–C11, C40
7
C12–C18,
C21–C25, C39,
C41
14
C19, C20
2
C26
1
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
MAX9205 Evaluation Kit
Evaluates: MAX9205–MAX9208
Component List (cont’d)
DESIGNATION
SYNC2,
PWRDN1,
DEN,
PWRDN2,
REN
TCLK,
REFCLK,
INA, INB
U1
U2
QTY
0
DESCRIPTION
Not installed, SMA PC-mount
edge connector
PART
TYPE
Part Selection Table
REF
CLOCK
RANGE
(MHz)
16 to 40
16 to 40
40 to 60
40 to 60
SERIAL DATA
TRANSFER
RATE (Mbps)
(max)
400
400
600
600
MAX9205EAI
4
1
1
SMA PC-mount edge
connectors
MAX9205EAI (28-pin SSOP)
MAX9206EAI (28-pin SSOP)
Buffer/driver three-state output
(48-pin TSSOP)
Texas Instruments
SN74ALVTH16244DGG
Shunts (JU1, JU3–JU7)
MAX9205 PC board
MAX9205 data sheet
MAX9205 EV kit data sheet
MAX9206EAI
MAX9207EAI
MAX9208EAI
Serializer
Deserializer
Serializer
Deserializer
U3
1
16MHz to 40MHz. Use LVCMOS/LVTTL levels. Note
that the TCLK SMA connector is terminated with a
50Ω resistor. Synchronize the pulse generator with
the data generator.
6) Set the data-acquisition system for LVCMOS/LVTTL-
level signal input.
7) Connect the data-acquisition system to the signal
output 24-pin connector J2. See Table 2 for output
bit locations.
8) Turn on the power supply.
9) Enable the pulse generator.
10) Enable the data generator.
11) Enable the data-acquisition system and begin sam-
pling data.
None
None
None
None
6
1
1
1
Quick Start
The MAX9205 EV kit is a fully assembled and tested
surface-mount board. Follow the steps below for EV kit
circuit board operation.
Do not turn on power supply
or enable the function generators until all connec-
tions are completed.
Recommended Equipment
• 3.3VDC power supply
• Data generator for LVCMOS/LVTTL 10-bit parallel
signal input (e.g., Tektronix DG2020)
• Clock pulse generator (e.g., HP 8130A)
• Logic analyzer or data-acquisition system
• High-speed oscilloscope
Detailed Description
The MAX9205 EV kit is a fully assembled and tested cir-
cuit board that simplifies the evaluation of the MAX9205
400Mbps maximum data transfer rate, 10-bit serializer
and the MAX9206 400Mbps maximum data transfer
data rate, 10-bit deserializer. The serializer/deserializer
data transfer starts with the serializer initially locking
onto the reference clock and then sending synchroniz-
ing patterns to the deserializer. Once the deserializer
locks onto the embedded clock in the patterns, it pulls
the SYNC pin low on the serializer, signaling that it is
ready to receive the serial data. The serializer trans-
forms the LVCMOS/LVTTL-level 10-bit parallel data pat-
tern into a serial high-speed BLVDS data stream. The
interconnect is terminated with 100Ω at each end of the
differential bus for a total 50Ω load. The MAX9206
deserializer accepts the serial data from the MAX9205
and transforms it back to 10-bit-wide LVCMOS/LVTTL
parallel data.
The EV kit requires a single 3.3V supply to operate and
a reference clock input in the 16MHz to 40MHz range.
The 10-bit parallel input data can be supplied to the 24-
pin header J1 with a data generator running at the
Procedure
1) Verify that there is a shunt across pins 1 and 2 of
jumpers JU1 and JU3–JU7.
2) Verify that JU2 does not have a shunt.
3) Connect the 3.3V power supply to VCC1. Connect
the ground terminal of this supply to GND1.
4) Connect the data generator to the 24-pin connector J1
and set it to generate 10-bit parallel data at
LVCMOS/LVTTL levels (high-level input from 2.0V to
VCC and low-level input from 0.8V to GND). See
Table 2 for input bit locations.
5) Connect the pulse generator to SMA connector
TCLK and set it for an output with a frequency of
2
_______________________________________________________________________________________
MAX9205 Evaluation Kit
same frequency as the reference clock or the bits can
be configured by installing shunts across header J1
pins. The output 10-bit parallel data can be sampled at
24-pin header J2 or individual bits can be tested at the
various 2-pin headers installed on the EV kit.
The EV kit circuit can be modified to isolate and evalu-
ate the MAX9205 and MAX9206 independently. While
isolated, the serializer’s output can be verified with a
differential probe or connected to category-5 twisted-
pair cable. The deserializer’s required LVDS input can
be supplied to the EV kit through category-5 twisted-
pair wire or SMA connectors.
The MAX9205 and MAX9206 serializer/deserializer pair
can be replaced with the MAX9207 and MAX9208 pair
for a higher maximum transfer speed rate of 600Mbps
with a maximum clock frequency of 60MHz.
Evaluates: MAX9205–MAX9208
Table 1. Clock Signal Monitoring Points
HEADER
JU14
JU15
SIGNAL
Clock input to
serializer
Clock input to
deserializer
CONNECTOR
Differential signal
probe
Differential signal
probe
Power Supplies
The MAX9205 EV kit operates from a single 3.3V power
supply. The serializer and deserializer power and
ground planes are connected with PC board traces
through resistor pads R49 and R50. The EV kit circuit
can be divided into two independent circuits, a serializ-
er and deserializer circuit with dedicated power and
ground planes, by cutting open the PC board shorting
traces at resistor pads R49 and R50. If the EV kit circuit
is divided into two separate circuits, each circuit
requires a 3.3V power supply connected at VCC1 (seri-
alizer circuit) and VCC2 (deserializer circuit).
Independent power and ground planes allow measure-
ments of the deserializer’s response to ground shift or
other common-mode effects. See the
Serializer/
Deserializer Circuits
section.
VCC and low-level input from 0.8V to GND). The 10-bit
pattern can be supplied to the EV kit by connecting a
data generator to the 24-pin header J1 or by pulling
selected J1 bit pins to a low LVCMOS/LVTTL state. All
the bit pins on J1 are pulled high (VCC1) with 10kΩ
pullup resistors installed on the 10 input signal lines.
See Table 2 for input bit locations on the 24-pin header
J1. If the serializer circuit is operated independently,
either the parallel input can be serialized or a sync pin
can be driven high to generate sync patterns. If the
deserializer is operated independently, a 12-bit serial
pattern (10 data bits plus 2 frame bits) must be sup-
plied to the deserializer circuit. Refer to the
Initialization
section in the MAX9206/MAX9208 data sheet for details
on the deserializer’s input requirements. See the
Serializer/Deserializer Circuits
section for further dis-
cussion of independent evaluation.
Output Signal
The MAX9205 EV kit outputs 10-bit parallel data at
LVCMOS/LVTTL levels on the 24-pin header J2. To
sample the 10-bit pattern, connect an acquisition sys-
tem to J2 or sample the individual bits with a 2-pin
header probe. See Table 2 for the output bits’ location
on the 24-pin header J2 or Table 3 for the location of
the individual output bits. The recovered clock signal is
located on pin 23 of J2 and can be used as the exter-
nal clock input for the acquisition system.
Clock Signal
The MAX9205 EV kit requires a square-wave
LVCMOS/LVTTL input clock signal with a frequency in
the 16MHz to 40MHz range. The clock signal can be
connected to the TCLK SMA connector or to pin 24 in
24-pin header J1. For faster data transfer rates, replace
the MAX9205 (U1) and MAX9206 (U2) serializer/deseri-
alizer pair with the MAX9207/MAX9208 serializer/dese-
rializer pair and supply a clock signal with a frequency
of 40MHz to 60MHz. During independent evaluation of
the serializer and deserializer, supply a clock signal to
each circuit. See the
Serializer/Deserializer Circuits
section. The clock input signal to the serializer and
deserializer can be monitored at 2-pin headers JU14
and JU15. See Table 1 for details.
Power-Down Reset
If no output signal is detected from the deserializer,
perform a power-down reset on the serializer by
momentarily pulling low the
PWRDN
pin using jumper
JU4. (See Table 5 for JU4 operation.)
Serializer/Deserializer Circuits
The MAX9205 EV kit board contains a 10-bit parallel
serializer (MAX9205)/deserializer (MAX9206) circuit
that only requires a 3.3V input power supply, a 10-bit
parallel pattern, an acquisition system, and a clock sig-
nal for simple board evaluation. JU2 is provided to test
the serializer high-impedance (Z) delay time. The EV kit
circuit can be divided into two circuits, a serializer and
a deserializer circuit, for independent evaluation. To di-
Input Signal
The MAX9205 EV kit accepts 10-bit parallel data at
LVCMOS/LVTTL levels (high-level input from 2.0V to
_______________________________________________________________________________________
3
MAX9205 Evaluation Kit
Evaluates: MAX9205–MAX9208
Table 2. Input/Output Bit Location
SIGNAL
Input/J1
Output/J2
BIT 0
J1-4
J2-1
BIT 1
J1-6
J2-3
BIT 2
J1-8
J2-5
BIT 3
J1-10
J2-7
BIT 4
J1-12
J2-9
BIT 5
J1-14
J2-11
BIT 6
J1-16
J2-13
BIT 7
J1-18
J2-15
BIT 8
J1-20
J2-17
BIT 9
J1-22
J2-19
Table 3. Individual Parallel Outputs
HEADER
JU16
JU17
JU18
JU19
JU20*
JU21*
JU22*
JU23
JU24
JU25
JU26*
JU27*
BIT/SIGNAL
0
1
2
3
4
5
6
7
8
9
LOCK
RCLK
Table 4. LVDS Signals and Connections
SIGNAL
NONINVERTING
SIGNAL
INVERTING
CONNECTOR
SIGNAL
Plated through
holes for
twisted- pair
(TP) cable
Differential
signal probe
Plated through
holes for TP
cable
Differential
signal probe
Serializer
(U1) Output
PC board
via 1A
PC board
via 1B
Serializer
(U1) Output
Deserializer
(U2) Input
Deserializer
(U2) Input
Header JU9
PC board
via 2A (user
input)
Header JU12
Header
JU10
PC board
via 2B (user
input)
Header
JU13
*
Headers are not in sequential order on the EV kit board.
vide the circuit into two circuits, cut open the PC board
trace shorting the resistor pads at R41–R45, R49, R50,
R75, remove resistor R39, and install a shorting resistor
on R48.
The MAX9205 (U1) serializer circuit generates two
types of signals, synchronization and serialized data
patterns:
1) Generate synchronization (SYNC) patterns by apply-
ing a high-state LVCMOS signal to pin 2 of the 24-
pin header J1 or the SYNC2 PC board pad.
2) Generate serialized data patterns by asserting a
low-state LVCMOS signal to pin 2 of the 24-pin
header J1 and provide 10-bit parallel data to the EV
kit. For data and clock input signal details, see the
Input Signal
and
Clock Signal
sections, respectively.
The serializer’s BLVDS output signal is a 12-bit serial
pattern that consists of a high-state start bit and low-
state end bit, added internally and used by the deseri-
alizer, to the 10-bit parallel input data. Refer to the
MAX9205/MAX9207 data sheet for details. To monitor
the BLVDS output signal, connect a differential signal
probe to JU9 (noninverting single-ended signal) or
JU10 (inverting single-ended signal) or connect twist-
ed-pair cable to PC board vias 1A (noninverting signal)
4
and 1B (inverting signal). Terminate the twisted pair at
the far end with a 100Ω resistor for a total 50Ω load.
See Table 4 for locations and connector type for the
LVDS serial signal output.
To evaluate the MAX9206 (U2) deserializer circuit, pro-
vide a 12-bit BLVDS serial input and a clock signal to
the REFCLK SMA connector. Bit 0 of the 12-bit serial
input pattern should be BLVDS high state and bit 11
should be BLVDS low state with data bit in between.
Refer to the MAX9206/MAX9208 data sheet for further
details on the start and end bits.
The 12-bit BLVDS pattern can be supplied to the dese-
rializer circuit in two ways: with twisted-pair cable or
SMA connectors:
1) Using twisted-pair cable, connect the serial input
signal to PC board vias 2A (noninverting signal) and
2B (inverting signal). Terminate the twisted-pair
cable at the transmitting end with a 100Ω resistor for
a total 50Ω load (including the 100Ω resistor in par-
allel at the deserializer input).
2) With SMA connectors, install shorting resistors at the
R46 and R47 PC board pads and connect the serial
signal through SMA connectors INA (noninverting
signal) and INB (inverting signal). Monitor the integri-
_______________________________________________________________________________________
MAX9205 Evaluation Kit
Evaluates: MAX9205–MAX9208
Table 5. Jumper Settings
JUMPER
JU1
JU2
JU3
JU4
SHUNT
STATUS
1 and 2
2 and 3
Installed
Open
1 and 2
2 and 3
1 and 2
2 and 3
1 and 2
JU5
2 and 3
1 and 2
2 and 3
1 and 2
2 and 3
PIN
CONNECTION
TCLK_R/
F
to VCC1
TCLK_R/
F
to GND1
None
None
DEN to VCC1
DEN to GND1
PWRDN
to VCC1
PWRDN
to GND1
REN to VCC2
REN to GND2
PWRDN
to VCC2
PWRDN
to GND2
RCLK_R/
F
to VCC2
RCLK_R/
F
to GND2
EV KIT
OPERATION
Serializer data loads on TCLK rising edge
Serializer data loads on TCLK falling edge
Common-mode voltage for serializer high-Z delay test
V
OS
(offset-voltage probe point)
Serial data output enabled
Serial data output in high-Z
Serializer in normal operation
Serializer in sleep mode, outputs in high-Z
Deserializer parallel outputs enabled
Deserializer ROUT0–ROUT9 and RCLK pins in high-Z,
LOCK
is active
Deserializer in normal operation
Deserializer outputs (all) in high-Z
Deserializer output data on RCLK rising edge
Deserializer output data on RCLK falling edge
JU6
JU7
Component Suppliers
SUPPLIER
AVX
Kemet
Murata
TDK
Texas Instruments
PHONE
843-448-9411
864-963-6300
770-436-1300
847-803-6100
972-644-5580
FAX
843-448-1943
864-963-6322
770-436-3030
847-390-6296
214-480-7800
WEBSITE
www.avxcorp.com
www.kemet.com
www.murata.com
www.component.tdk.com
www.ti.com
Note:
Please indicate that you are using the MAX9205 when contacting these component suppliers.
ty of the LVDS input signal by connecting a differen-
tial signal probe to jumpers JU12 (noninverting sig-
nal) or JU13 (inverting signal). See Table 4 for loca-
tions and connector type for the serial input. To eval-
uate the output signal of the deserializer, see the
Output Signal
section. If
LOCK
is not low (check
JU26 or J2-23), send 200 or more synchronization
patterns to the deserializer to lock onto the serial
input.
Terminations and Layout
All signal lines are 50Ω controlled-impedance traces. All
the differential output signal traces are terminated with
100Ω resistors at each end. Each differential output pair
is laid out with equal trace length. The EV kit is laid out
as a four-layer board to minimize noise interference.
Jumper Settings
The MAX9205 EV kit circuit contains several jumpers
that allow the user to put the serializer and deserializer
into several operational modes. See Table 5 for jumper
settings and EV kit operation descriptions.
_______________________________________________________________________________________
5
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