DLP-HS-FPGA
DLP-HS-FPGA2
LEAD FREE
USB - FPGA MODULE
FEATURES
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Xilinx XC3S200A-4FTG256C FPGA utilized on the DLP-HS-FPGA
Xilinx XC3S400A-4FTG256C FPGA utilized on the DLP-HS-FPGA2
Micron 32M x 8 DDR2 SDRAM Memory
Built-In Configuration Loader; Writes the Bit File Directly to SPI Flash via High-Speed USB 2.0
Interface
63 User I/O Channels: 24 Differential Pairs and 8 Global Clocks
66.666 MHz Oscillator
133 MHz DDR2 Interface Reference Design Provided
USB Port Powered or 5V External Power Barrel Jack
USB 1.1 and 2.0 Compatible Interface
Small Footprint: 3.0 x 1.2-Inch PCB and Standard 50-Pin, 0.9-Inch DIP Interface
Rev. 2.1 (April 2012)
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© DLP Design, Inc.
APPLICATIONS:
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Rapid Prototyping
Educational Tool
Industrial/Process Control
Data Acquisition/Processing
Embedded Processor
1.0 INTRODUCTION
The DLP-HS-FPGA module is a low-cost, compact prototyping tool that can be used for rapid proof of
concept or within educational environments. The module is based on the Xilinx Spartan™ 3A and
Future Technology Devices International’s FT2232H Dual-Channel High-Speed USB IC. The
DLP-HS-FPGA provides both the beginner as well as the experienced engineer with a rapid path to
developing FPGA-based designs. When combined with the free ISE™ WebPACK™ tools from Xilinx,
this module is more than sufficient for creating anything from basic logical functions to a highly
complex system controller.
As a bonus feature, one channel of the dual-channel USB interface is used to load user bit files
directly to the SPI Flash—no external programmer is required. This represents a savings of as much
as $200 in that no additional programming cable is required for configuring the FPGA. All that is
needed to load bit files to the DLP-HS-FPGA is a Windows software utility (free with purchase), a
Windows PC and a USB cable. The module can also be programmed from within the Xilinx ISE tool
environment using a Xilinx programming cable (purchased separately).
The DLP-HS-FPGA is fully compatible with the free ISE™ WebPACK™ tools from Xilinx. ISE
WebPACK offers the ideal development environment for FPGA designs with HDL synthesis and
simulation, implementation, device fitting and JTAG programming.
The DLP-HS-FPGA has on-board voltage regulators that generate all required power supply voltages
from a single 5-volt source. Power for the module can be taken from either the host USB port or from
a user-supplied, external 5-volt power supply via an onboard standard barrel connector.
Connection to user electronics is made via a 50-pin, 0.9-inch wide, industry-standard 0.025-square
inch post DIP header on the bottom of the board and a 26-pin, 0.05-inch wide top side 2x13 header.
The bottom side 50-pin header provides access to 41 of the FPGA user input/output pins. The top
side header provides access to 22 of the FPGA user input/output pins. The bottom side header mates
with a user-supplied, standard, 50-pin, 0.9-inch spaced DIP socket. The top side header mates with a
user-supplied, 0.05-inch spaced, 2x13 connector such as the FFSD-13-D-xx.xx-01 (xx.xx = cable
length) ribbon cable assembly from Samtec.
Rev. 2.1 (April 2012)
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DIP Socket
Ribbon Cable
Other on-board features include a 32M x 8 DDR2 SDRAM memory IC for user projects and both
JTAG and SPI Flash interface ports for connection to Xilinx programming tools.
2.0 REFERENCE DESIGN
A 10,000-line reference design is available for the Spartan™ 3A FPGA on the DLP-HS-FPGA to those
who purchase the module. The design was written in VHDL and built using the free Xilinx ISE™
WebPACK™ tools. The reference design consists of the following blocks:
It contains a USB Interface Block, a User I/0 Block, a DDR2 SDRAM interface, a Heartbeat Pulse
Generator and a Clock Generator. The SPI Flash is used to store the design’s FPGA configuration
file.
The USB interface captures, interprets and returns command and data information sent from the host
PC through the FTDI USB interface to the FPGA. Commands include Ping, Return Status, Loopback
Data, Set a User I/O Pin High or Low, Read a User I/O Pin, Initialize the DDR2 SDRAM Memory and
Read or Write the DDR2 SDRAM Memory. (Section 11 explains these in detail.)
The User I/O Block controls access to the 63 user I/O pins accessible through the top- and bottom-
side headers. Every one of these pins can be either an input or an output. The User I/O Block can
configure these pins as inputs and read their state, or as outputs and drive them high or low. (As a
side note, 48 of these user I/O pins can be configured as 24 differential pairs, 8 can be configured as
global clock inputs and 6 can be configured as regional clock inputs.)
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© DLP Design, Inc.
The DDR2 SDRAM interface block manages the memory’s initialization, the refresh cycle and the
read and write access. Read and write access is available in 4-byte bursts. The traces between the
DDR2 SDRAM and FPGA are matched within 10 mils to accommodate reliable data transfer at 266
Mbit/s (clocked at 133MHz). The interface creates and aligns the Data Strobes (DQS) based on an
external feedback trace that matches two times the trace length between the FPGA and the DDR2
SDRAM. The Initialization, Read and Write commands are initiated by the USB interface block and
executed by the DDR2 SDRAM interface block.
The Heartbeat Pulse Generator takes the internal system clock and divides it down so that the
onboard Heartbeat LED will be turned on and off for a duration of approximately one-half second.
The Clock Generator Block receives the 66.666-MHz clock and produces both the 133-MHz clocks
required to run the DDR2 SDRAM memory device and the 100-MHz clock for the remaining internal
logic in the FPGA. It also handles reset and lock synchronization between internal DCM blocks.
The design occupies the following FPGA resources on the DLP-HS-FPGA module’s XC3S200A:
The design occupies the following FPGA resources on the DLP-HS-FPGA2 module’s XC3S400A:
More reference designs are planned. Please contact DLP Design with any specific requests.
Rev. 2.1 (April 2012)
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© DLP Design, Inc.
3.0 FPGA SPECIFICATIONS
The FPGA device used on the DLP-HS-FPGA is the Xilinx Spartan™ 3A: XC3S200A-4FTG256
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Part Number:
System Gates:
Equivalent Logic Cells:
CLB Array:
Rows:
Columns:
Total CLB’s:
Total Slices:
Total Flip Flops:
Total 4-Input LUT’s:
XC3S200A-4FTG256C
200,000
4,032
32
16
448
1,792
3,584
3,584
28K
288K
16
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Distributed RAM Bits:
Block RAM Bits:
Dedicated Multipliers:
DCM’s:
The FPGA device used on the DLP-HS-FPGA2 is the Xilinx Spartan™ 3A: XC3S400A-4FTG256
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Part Number:
System Gates:
Equivalent Logic Cells:
CLB Array:
Rows:
Columns:
Total CLB’s:
Total Slices:
Total Flip Flops:
Total 4-Input LUT’s:
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Distributed RAM Bits:
40
24
896
3,584
7,168
7,168
56K
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© DLP Design, Inc.
XC3S400A-4FTG256C
400,000
8,064
Rev. 2.1 (April 2012)
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