PRELIMINARY INFORMATION
MK2049-36
3.3 V Communications Clock PLL
Features
• Packaged in 20 pin SOIC
• 3.3 V ±5% operation
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
• Accepts multiple inputs: 8 kHz backplane clock,
or 10 to 50 MHz
• Locks to 8 kHz ±100 ppm (External mode)
• Buffer Mode allows jitter attenuation of
10-50 MHz input and x1/x0.5 or x1/x2 outputs
• Exact internal ratios enable zero ppm error
• Output clock rates include T1, E1, T3, E3,
and OC3 submultiples
• See the MK2049-01, -02, and -03 for more
selections at VDD = 5 V, and the MK2049-34 for
more selections at 3.3 V
Description
The MK2049-36 is a Phase-Locked Loop (PLL)
based clock synthesizer that accepts multiple input
frequencies. With an 8 kHz clock input as a
reference, the MK2049-36 generates T1, E1, T3,
E3, OC3/3, Gigabit Ethernet, and other
communications frequencies. This allows for the
generation of clocks frequency-locked to an 8 kHz
backplane clock, simplifying clock synchronization
in communications systems.
This part also has a jitter-attenuated Buffer
capability. In this mode, the MK2049-36 is ideal
for filtering jitter from with high jitter clocks.
ICS can customize these devices for many other
different frequencies. Contact your ICS
representative for more details.
Block Diagram
VDD
3
GND
3
RES
FS3:0
4
Clock
Input
Reference
X1
Crystal
Crystal
Oscillator
X2
External/
Buffer Mode
Mux
PLL
Clock
Synthesis,
Control, and
Jitter
Attenuation
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
CLK
CLK/2
8 kHz
(External
Mode only)
FCAP
CAP1
CAP2
1
Revision 120400
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2049-36 A
PRELIMINARY INFORMATION
MK2049-36
3.3 V Communications Clock PLL
Pin Assignment
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8K
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
FS0
RES
CAP2
GND
CAP1
VDD
GND
ICLK
FS3
FS2
20 pin (300 mil) SOIC
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8K
FS2
FS3
ICLK
GND
VDD
CAP1
GND
CAP2
RES
FS0
Type
I
XO
XI
P
-
P
P
O
O
O
I
I
I
P
P
LF
P
LF
-
I
Description
Frequency Select 1. Determines CLK input/outputs per tables on page 4.
Crystal connection. Connect to a MHz crystal as shown in the tables on page 4.
Crystal connection. Connect to a MHz crystal as shown in the tables on page 4.
Connect to +3.3V.
Filter Capacitor. Connect a 1000 pF ceramic capacitor to ground.
Connect to +3.3V.
Connect to ground.
Clock output determined by status of FS3:0 per tables on page 4.
Clock output determined by status of FS3:0 per tables on page 4. Always 1/2 of CLK.
Recovered 8 kHz clock output.
Frequency Select 2. Determines CLK input/outputs per tables on page 4.
Frequency Select 3. Determines CLK input/outputs per tables on page 4.
Input clock connection. Connect to 8 kHz backplane or MHz clock.
Connect to ground.
Connect to +3.3V.
Connect the loop filter ceramic capacitors and resistor between this pin and CAP2.
Connect to ground.
Connect the loop filter ceramic capacitors and resistor between this pin and CAP1.
Connect a 10-200kΩ resistor to ground. Contact ICS applications dept. at 408-297-1201 for the recommended value for your app.
Frequency Select 0. Determines CLK input/outputs per tables on page 4.
Type: XI, XO = crystal connections, I = Input, O = output, P = power supply connection, LF = loop filter
connections
2
Revision 120400
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2049-36 A
PRELIMINARY INFORMATION
MK2049-36
3.3 V Communications Clock PLL
Electrical Specifications
Parameter
Supply Voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage Temperature
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage, VOH, CMOS level
Output High Voltage, VOH
Output Low Voltage
Operating Supply Current, IDD
Short Circuit Current
Input Capacitance, FS3:0
Input Frequency, External Mode
Input Clock Pulse Width
Propagation Delay
Delay, CLK/2 after CLK
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle, High Time
Actual mean frequency error versus target
Conditions
Referenced to GND
-0.5
-40
Max of 10 seconds
-65
3.15
2
IOH=-4 mA
IOH=-8 mA
IOL=8 mA
No Load, VDD=3.3 V
Each output
VDD-0.4
2.4
0.4
7
±50
5
8.000
10
ICLK to 8 kHz
0.8 to 2.0 V
2.0 to 0.8 V
At VDD/2, except 8k
Any clock selection
7
1
2
2
60
0
3.3
Minimum
Typical
Maximum
7
VDD+0.5
85
250
150
3.45
0.8
Units
V
V
°C
°C
°C
V
V
V
V
V
V
mA
mA
pF
kHz
ns
ns
ns
ns
ns
%
ppm
ABSOLUTE MAXIMUM RATINGS (Note 1)
DC CHARACTERISTICS (VDD = 3.3 V unless noted)
AC CHARACTERISTICS (VDD = 3.3 V unless noted)
ICLK
40
0
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
3
Revision 120400
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2049-36 A
PRELIMINARY INFORMATION
MK2049-36
3.3 V Communications Clock PLL
8K
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
TEST
8 kHz
8 kHz
8 kHz
TEST
8 kHz
8 kHz
Crystal
12.352
12.288
11.184
11.456
19.44
16.384
14.352
TEST
18.528
24.704
15.36
TEST
24.576
12.288
MK2049-36 Output Decoding Table – External Mode (MHz)
ICLK
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK/2
1.544
2.048
22.368
17.184
77.76
16.384
14.352
TEST
18.528
12.352
7.68
TEST
12.288
16.384
CLK
3.088
4.096
44.736
34.368
155.52
32.768
28.704
TEST
37.056
24.704
15.36
TEST
24.576
32.768
MK2049-36 Output Decoding Table – Buffer Mode (MHz)
ICLK
22 - 36
11 - 18
FS3 FS2 FS1 FS0
1
1
1
0
1
1
1
1
CLK/2
ICLK/2
2*ICLK
CLK
ICLK
4*ICLK
8K
N/A
N/A
Crystal
ICLK/2
ICLK
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
4
Revision 120400
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2049-36 A
PRELIMINARY INFORMATION
MK2049-36
3.3 V Communications Clock PLL
OPERATING MODES
The MK2049-36 has two operating modes: External and Buffer. Although both modes use an input clock
to generate various output clocks, there are important differences in their input and crystal requirements.
External Mode
The MK2049-36 accepts an external 8 kHz clock and will produce a number of common communication
clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse
as narrow as 10 ns is acceptable.
Buffer Mode
Unlike the other mode that accepts only a single specified input frequency, Buffer Mode will accept a wider
range of input clocks. The input jitter is attenuated, and the outputs on CLK and CLK/2 also provide the
option of getting x1, x2, x4, or 1/2 of the input frequency. For example, this mode can be used to remove
the jitter from a 27 MHz clock, generating low-jitter 27 MHz and 13.5 MHz outputs.
FREQUENCY LOCKING TO THE INPUT
In all modes, the output clocks are frequency-locked to the input. The output will remain at the specified
output frequency as long as the combined variation of the input frequency and the crystal does not exceed
100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the
input frequency can vary by up to 60 ppm and still have the output clock remain frequency-locked.
5
Revision 120400
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MDS 2049-36 A
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