CMOS 300 MSPS Quadrature
Complete DDS
AD9854
FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit digital-to-analog converters (DACs)
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz (±1 MHz) A
OUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and
on/off output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via input/output interface
Linear or nonlinear FM chirp functions with single-pin
frequency hold function
Frequency-ramped FSK
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interfaces
10 MHz serial 2- or 3-wire SPI compatible
100 MHz parallel 8-bit programming
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad
APPLICATIONS
Agile, quadrature LO frequency synthesis
Programmable clock generators
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciters
FUNCTIONAL BLOCK DIAGRAM
SYSTEM CLOCK
FREQUENCY
ACCUMULATOR
ACC 1
PHASE
ACCUMULATOR
ACC 2
48
48
17
17
PHASE-TO-
AMPLITUDE
CONVERTER
MUX
REFERENCE
CLOCK IN
REF
CLK
BUFFER
4× TO 20×
REF CLK
MULTIPLIER
DDS CORE
I
MUX
12
INV
SINC
FILTER
DIGITAL MULTIPLIERS
12
12-BIT
I
DAC
ANALOG
OUT
DAC R
SET
12-BIT
Q DAC OR
CONTROL
DAC
ANALOG
OUT
DIFF/SINGLE
SELECT
SYSTEM
CLOCK
Q
DEMUX
FSK/BPSK/HOLD
DATA IN
3
MUX
DELTA
FREQUENCY
RATE TIMER
2
48 SYSTEM
CLOCK
DELTA
FREQUENCY
WORD
48
48
14
MUX
MUX
SYSTEM
CLOCK
14
12
12
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
12
12
COMPARATOR
CLOCK
OUT
ANALOG
IN
FREQUENCY
TUNING
WORD 1
I AND Q 12-BIT
FREQUENCY
FIRST 14-BIT
SECOND 14-BIT
12-BIT DC
TUNING
PHASE/OFFSET PHASE/OFFSET AM MODULATION CONTROL
WORD 2
WORD
WORD
PROGRAMMING REGISTERS
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE CLOCK
MODE SELECT
SYSTEM
CK
CLOCK
Q
D
INT
EXT
MUX
48
14
MUX
SYSTEM
CLOCK
MUX
12
INV
SINC
FILTER
12
OSK
BUS
I/O PORT BUFFERS
GND
+V
S
÷2
SYSTEM
CLOCK
AD9854
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
READ
WRITE
SERIAL/
PARALLEL
SELECT
Figure 1.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2007 Analog Devices, Inc. All rights reserved.
00636-001
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
AD9854* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DOCUMENTATION
Application Notes
•
AN-1389: Recommended Rework Procedure for the Lead
Frame Chip Scale Package (LFCSP)
•
AN-237: Choosing DACs for Direct Digital Synthesis
•
AN-280: Mixed Signal Circuit Technologies
•
AN-342: Analog Signal-Handling for High Speed and
Accuracy
•
AN-345: Grounding for Low-and-High-Frequency Circuits
•
AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal
Oscillator for the AD9850
•
AN-423: Amplitude Modulation of the AD9850 Direct
Digital Synthesizer
•
AN-543: High Quality, All-Digital RF Frequency
Modulation Generation with the ADSP-2181 and the
AD9850 DDS
•
AN-557: An Experimenter's Project:
•
AN-587: Synchronizing Multiple AD9850/AD9851 DDS-
Based Synthesizers
•
AN-605: Synchronizing Multiple AD9852 DDS-Based
Synthesizers
•
AN-621: Programming the AD9832/AD9835
•
AN-632: Provisionary Data Rates Using the AD9951 DDS as
an Agile Reference Clock for the ADN2812 Continuous-
Rate CDR
•
AN-769: Generating Multiple Clock Outputs from the
AD9540
•
AN-772: A Design and Manufacturing Guide for the Lead
Frame Chip Scale Package (LFCSP)
•
AN-823: Direct Digital Synthesizers in Clocking
Applications Time
•
AN-837: DDS-Based Clock Jitter Performance vs. DAC
Reconstruction Filter Performance
•
AN-843: Measuring a Loudspeaker Impedance Profile
Using the AD5933
•
AN-847: Measuring a Grounded Impedance Profile Using
the AD5933
•
AN-851: A WiMax Double Downconversion IF Sampling
Receiver Design
•
AN-927: Determining if a Spur is Related to the DDS/DAC
or to Some Other Source (For Example, Switching
Supplies)
EVALUATION KITS
•
AD9854 Evaluation Board
•
AN-939: Super-Nyquist Operation of the AD9912 Yields a
High RF Output Signal
•
AN-953: Direct Digital Synthesis (DDS) with a
Programmable Modulus
Data Sheet
•
AD9854: CMOS 300 MSPS Quadrature Complete DDS Data
Sheet
Product Highlight
• Introducing Digital Up/Down Converters: VersaCOMM™
Reconfigurable Digital Converters
Technical Books
•
A Technical Tutorial on Digital Signal Synthesis, 1999
DESIGN RESOURCES
•
AD9854 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
DISCUSSIONS
View all AD9854 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TOOLS AND SIMULATIONS
•
ADIsimDDS (Direct Digital Synthesis)
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
REFERENCE MATERIALS
Product Selection Guide
•
RF Source Booklet
Technical Articles
•
400-MSample DDSs Run On Only +1.8 VDC
•
ADI Buys Korean Mobile TV Chip Maker
•
Basics of Designing a Digital Radio Receiver (Radio 101)
•
DDS Applications
•
DDS Circuit Generates Precise PWM Waveforms
•
DDS Design
•
DDS Device Produces Sawtooth Waveform
•
DDS Device Provides Amplitude Modulation
•
DDS IC Initiates Synchronized Signals
•
DDS IC Plus Frequency-To-Voltage Converter Make Low-
Cost DAC
•
DDS Simplifies Polar Modulation
•
Digital Potentiometers Vary Amplitude In DDS Devices
• Digital Up/Down Converters: VersaCOMM™ White Paper
•
Digital Waveform Generator Provides Flexible Frequency
Tuning for Sensor Measurement
•
Improved DDS Devices Enable Advanced Comm Systems
•
Integrated DDS Chip Takes Steps To 2.7 GHz
•
Simple Circuit Controls Stepper Motors
•
Speedy A/Ds Demand Stable Clocks
•
Synchronized Synthesizers Aid Multichannel Systems
•
The Year of the Waveform Generator
•
Two DDS ICs Implement Amplitude-shift Keying
•
Video Portables and Cameras Get HDMI Outputs
DOCUMENT FEEDBACK
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AD9854
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications..................................................................................... 5
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
Explanation of Test Levels ........................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 12
Typical Applications ....................................................................... 16
Theory of Operation ...................................................................... 19
Modes of Operation ................................................................... 19
Using the AD9854 .......................................................................... 29
Internal and External Update Clock ........................................ 29
On/Off Output Shaped Keying (OSK) .................................... 29
I and Q DACs.............................................................................. 30
Control DAC ............................................................................... 30
Inverse Sinc Function ................................................................ 31
REFCLK Multiplier .................................................................... 31
Programming the AD9854............................................................ 32
MASTER RESET ........................................................................ 32
Parallel I/O Operation ............................................................... 34
Serial Port I/O Operation.......................................................... 34
General Operation of the Serial Interface ................................... 36
Instruction Byte .......................................................................... 37
Serial Interface Port Pin Descriptions ..................................... 37
Notes on Serial Port Operation ................................................ 37
MSB/LSB Transfers......................................................................... 38
Control Register Description.................................................... 38
Power Dissipation and Thermal Considerations ....................... 40
Thermal Impedance................................................................... 40
Junction Temperature Considerations .................................... 40
Evaluation of Operating Conditions........................................ 41
Thermally Enhanced Package Mounting Guidelines ................ 41
Evaluation Board ............................................................................ 42
Evaluation Board Instructions.................................................. 42
General Operating Instructions ............................................... 42
Using the Provided Software .................................................... 44
Support ........................................................................................ 44
Outline Dimensions ....................................................................... 52
Ordering Guide .......................................................................... 52
Rev. E | Page 2 of 52
AD9854
REVISION HISTORY
7/07—Rev. D to Rev. E
Changed AD9854ASQ to AD9854ASVZ ....................... Universal
Changed AD9854AST to AD9854ASTZ......................... Universal
Changes to General Description .....................................................4
Changes to Table 1 Endnotes...........................................................7
Changes to Absolute Maximum Ratings Section..........................8
Changes to Power Dissipation Section.........................................40
Changes to Thermally Enhanced Package Mounting
Guidelines Section......................................................................41
Changes to Figure 64 ......................................................................47
Changes to Outline Dimensions ...................................................52
Changes to Ordering Guide...........................................................52
11/06—Rev. C to Rev. D
Changes to General Description Section .......................................4
Changes to Endnotes in the Power Supply Parameter .................7
Changes to Absolute Maximum Ratings Section..........................8
Added Endnotes to Table 2 ..............................................................8
Changes to Figure 50 ......................................................................29
Changes to Power Dissipation Section.........................................39
Changes to Figure 68 ......................................................................45
Updated Outline Dimensions........................................................51
Changes to Ordering Guide...........................................................51
9/04—Rev. B to Rev. C
Updated Format.................................................................. Universal
Changes to Table 1 ............................................................................4
Changes to Footnote 2 ......................................................................7
Changes to Explanation of Test Levels Section .............................8
Changes to Theory of Operation Section ....................................17
Changes to Single Tone (Mode 000) Section...............................17
Changes to Ramped FSK (Mode 010) Section............................18
Changes to Basic FM Chirp Programming Steps Section .........23
Changes to Figure 50 ......................................................................27
Changes to Evaluation Board Operating Instructions Section.40
Changes to Filtered IOUT1 and the Filtered IOUT2 Section ...41
Changes to Using the Provided Software Section.......................42
Changes to Figure 68 ......................................................................45
Changes to Figure 69 ......................................................................46
Updated Outline Dimensions........................................................50
Changes to Ordering Guide...........................................................50
3/02—Rev. A to Rev. B
Updated Format ................................................................. Universal
Renumbered Figures and Tables ...................................... Universal
Changes to General Description Section.......................................1
Changes to Functional Block Diagram ..........................................1
Changes to Specifications Section ..................................................4
Changes to Absolute Maximum Ratings Section .........................7
Changes to Pin Function Descriptions ..........................................8
Changes to Figure 3 ........................................................................10
Deleted two Typical Performance Characteristics Graphs........11
Changes to Inverse SINC Function Section ................................28
Changes to Differential REFCLK Enable Section.......................28
Changes to Figure 52 ......................................................................30
Changes to Parallel I/O Operation Section .................................32
Changes to General Operation of the Serial Interface Section .33
Changes to Figure 57 ......................................................................34
Replaced Operating Instructions Section ....................................40
Changes to Figure 68 ......................................................................44
Changes to Figure 69 ......................................................................45
Changes to Customer Evaluation Board Table............................46
Rev. E | Page 3 of 52
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