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74LVX27M

Description
LOW VOLTAGE CMOS TRIPLE 3 INPUT NOR GATE WITH 5V TOLERANT INPUTS
Categorylogic    logic   
File Size89KB,8 Pages
ManufacturerSTMicroelectronics
Websitehttp://www.st.com/
Environmental Compliance
Download Datasheet Parametric View All

74LVX27M Overview

LOW VOLTAGE CMOS TRIPLE 3 INPUT NOR GATE WITH 5V TOLERANT INPUTS

74LVX27M Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSTMicroelectronics
Parts packaging codeSOIC
package instructionSOP, SOP14,.25
Contacts14
Reach Compliance Codecompli
seriesLV/LV-A/LVX/H
JESD-30 codeR-PDSO-G14
JESD-609 codee4
length8.65 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeNOR GATE
MaximumI(ol)0.004 A
Humidity sensitivity level1
Number of functions3
Number of entries3
Number of terminals14
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTUBE
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Su12.5 ns
propagation delay (tpd)17 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)2.7 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width3.9 mm
Base Number Matches1
74LVX27
LOW VOLTAGE CMOS TRIPLE 3-INPUT NOR GATE
WITH 5V TOLERANT INPUTS
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED :
t
PD
= 4.1ns (TYP.) at V
CC
= 3.3V
5V TOLERANT INPUTS
INPUT VOLTAGE LEVEL :
V
IL
=0.8V, V
IH
=2V at V
CC
=3V
LOW POWER DISSIPATION:
I
CC
= 2
µA
(MAX.) at T
A
=25°C
LOW NOISE:
V
OLP
= 0.3V (TYP.) at V
CC
= 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 27
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS
SOP
TSSOP
ORDER CODES
PACKAGE
SOP
TSSOP
TUBE
74LVX27M
T&R
74LVX27MTR
74LVX27TTR
DESCRIPTION
The 74LVX27 is a low voltage CMOS TRIPLE
3-INPUT NOR GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
PIN CONNECTION AND IEC LOGIC SYMBOLS
The internal circuit is composed of 3 stages
including buffer output, which provides high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
July 2001
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