ADRF6655-EVALZ datasheet, PDF - EEWORLD Datasheet

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ADRF6655-EVALZ: DescriptionCrystals 32.768KHz 12.5pf 3.2 x 1.5 x 0.9mm; CategoryDevelopment board/suite/development tools; File Size3MB，42 Pages; ManufacturerADI; Websitehttps://www.analog.com

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Crystals 32.768KHz 12.5pf 3.2 x 1.5 x 0.9mm

ADRF6655-EVALZ Parametric

Parameter Name	Attribute value
Product Category	RF Development Tools
Manufacturer	ADI
RoHS	Details
Product	Evaluation Boards
Type	RF Mixers
Tool Is For Evaluation Of	ADRF6655
Frequency	100 MHz to 2.5 GHz
Operating Supply Voltage	5 V
Packaging	Bulk
Interface Type	SMA Connector
Factory Pack Quantity	1

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Data Sheet

FEATURES

Broadband Up/Downconverting Mixer with

Integrated Fractional-N PLL and VCO

ADRF6655

The programmable divider is controlled by an Σ-Δ modulator

(SDM). The modulus of the SDM can be programmed between

1 and 2047.

The broadband, active mixer employs a bias adjustment to allow

for enhanced IP3 performance at the expense of increased supply

current. The mixer provides an input IP3 exceeding 25 dBm

with 12 dB single sideband NF under typical conditions. The IIP3

can be boosted to ~29 dBm with roughly 20 mA of additional

supplied current. The mixer provides a typical voltage conversion

gain of 6 dB with a 200 Ω differential IF output impedance. The

IF output can be externally matched to support upconversion over

a limited frequency range.

The

ADRF6655

is fabricated using an advanced silicon-

germanium BiCMOS process. It is packaged in a 40-lead,

exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP. Performance is

specified over a −40°C to +85°C temperature range.

Broadband active mixer with integrated fractional-N PLL

RF input frequency range: 100 MHz to 2500 MHz

Internal LO frequency range: 1050 MHz to 2300 MHz

Flexible IF output interface

Input P1dB: 12 dBm

Input IP3: 29 dBm

Noise figure (SSB): 12 dB

Voltage conversion gain: 6 dB

Matched 200 Ω output impedance

SPI serial interface for PLL programming

40-lead 6 mm × 6 mm LFCSP

GENERAL DESCRIPTION

The

ADRF6655

is a high dynamic range active mixer with

integrated PLL and VCO. The synthesizer uses a programmable

integer-N/fractional-N PLL to generate a local oscillator input

to the mixer. The PLL reference input is nominally 20 MHz. The

reference input can be divided by or multiplied by and then

applied to the PLL phase detector. The PLL can support input

reference frequencies from 10 MHz to 160 MHz. The phase

detector output controls a charge pump whose output is integrated

in an off-chip loop filter. The loop filter output is then applied to an

integrated VCO. The VCO output at 2 × f

is then applied to a local

oscillator (LO) divider as well as to a programmable PLL divider.

FUNCTIONAL BLOCK DIAGRAM

GND

VCCLO

GND

LOSEL

LON

BUFFER

GND

IP3SET

GND

VCCMIX

INP

INN

ADRF6655

LOP

FRACTION MODULUS

REG

SPI

INTERFACE

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

N COUNTER

21 TO 123

×2

REFIN

GND

÷2

÷4

3.3V LDO

MUXOUT

GND

DATA

CLK

GND

INTEGER

REG

LOSEL

BUFFER

MUX

DIVIDER

÷2 OR ÷3

PRESCALER

VCO

CORE

GND

VCCV2I

GND

MUX

TEMP

SENSOR

–

PHASE

+ FREQUENCY

DETECTOR

CHARGE PUMP

250µA,

500µA (DEFAULT),

750µA,

1000µA

2.5V LDO

VCO LDO

08817-001

VCC1

DECL1

GND RSET DECL2 VCC2 VTUNE DECL3 NC VCCLO OUTN OUTP GND

Figure 1.

Rev. A

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

ADRF6655

TABLE OF CONTENTS

Features .............................................................................................. 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Despcriptions .......................... 7

Typical Performance Characteristics ............................................. 9

Downconversion ........................................................................... 9

Upconversion .............................................................................. 11

PLL Characteristic ...................................................................... 12

Complimentary Cumulative Distribution Function (CCDF):

Downconversion, LO = 1100 MHz, RF = 900 MHz .............. 14

Complimentary Cumulative Distribution Function (CCDF):

Downconversion, LO = 1700 MHz, RF = 1900 MHz ............ 15

Complimentary Cumulative Distribution Function (CCDF):

Upconversion Distribution ....................................................... 16

Circuit Description ......................................................................... 17

PLL and VCO Block ................................................................... 17

RF Mixer Block ........................................................................... 17

Digital Interfaces ........................................................................ 18

Analog Interfaces ............................................................................ 19

Supply Connections ................................................................... 19

Synthesizer Connections ........................................................... 19

Data Sheet

Output Matching and Biasing .................................................. 19

Input Matching ........................................................................... 20

IP3SET Linearization Feature ................................................... 21

CDAC Linearization Feature .................................................... 21

External LO Interface ................................................................ 21

Using an External VCO ............................................................. 22

ADRF6655 Control Software ........................................................ 23

PLL Loop Filter Design ............................................................. 23

Device Programming ................................................................. 25

Initialization Sequence .............................................................. 25

Path Control ................................................................................ 29

Characterization Setups ................................................................. 34

Evaluation Board Layout and Thermal Grounding ................... 38

Outline Dimensions ....................................................................... 41

Ordering Guide .......................................................................... 41

REVISION HISTORY

9/14—Rev. 0 to Rev. A

Changes to Figure 3 .......................................................................... 7

Changes to Table 4 ............................................................................ 8

Changes to ADRF6655 Control Software Section, Figure 66,

and Figure 67 ................................................................................... 23

Updated Outline Dimensions ....................................................... 41

2/10—Revision 0: Initial Version

Rev. A | Page 2 of 41

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