ADVANCE
‡
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, QDRIIb4 SRAM
18Mb QDR™II SRAM
4-Word Burst
FEATURES
• 18Mb Density (2 Meg x 8, 1 Meg x 18, 512K x 36)
• DLL circuitry for wide-output, data valid window
and future frequency scaling
• Separate independent read and write data ports with
concurrent transactions
• 100% bus utilization DDR READ and WRITE
operation
• Fast clock to valid data times
• Full data coherency, providing most current data
• Four-tick burst for reduced-address frequency
• Double data rate operation on read and write ports
• Two input clocks (K and K#) for precise DDR timing
at clock rising edges only
• Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
• Single address bus
• Simple control logic for easy depth expansion
• Internally self-timed, registered writes
• +1.8V core and HSTL I/O
• Clock-stop capability with
ms
restart
• 13x15mm, 1mm pitch, 11 x 15 grid FBGA package
• User programmable impedance output
• JTAG boundary scan
MT54W2MH8J
MT54W1MH18J
MT54W512H36J
165-BALL FBGA
GENERAL DESCRIPTION
The Micron
®
QDR™II (Quad Data Rate™) synchro-
nous, pipelined, burst SRAM employs high-speed, low-
power CMOS designs using an advanced 6T CMOS pro-
cess. The QDR architecture consists of two separate DDR
(double data rate) ports to access the memory array. The
read port has dedicated data outputs to support READ
operations. The write port has dedicated data inputs to
support WRITE operations. This architecture eliminates
the need for high-speed bus turnaround. Access to each
port is accomplished using a common address bus. Ad-
dresses for reads and writes are latched on rising edges of
the K and K# input clocks, respectively. Each address
location is associated with four data words that burst
sequentially into or out of the device. Since data can be
transferred into
and
out of the device on every rising edge
of both clocks (K, K#, C and C#), memory bandwidth is
maximized while simplifying system design by eliminat-
ing bus turnarounds.
Depth expansion is accomplished with port selects
for each port (read R#, write W#) which are received at K
rising edge. Port selects permit independent port opera-
tion. All synchronous inputs pass through registers con-
trolled by the K or K# input clock rising edges. Active LOW
byte writes (BWx#) permit byte or nybble write selection.
Write data and byte writes are registered on the rising
edges of both K and K#. The addressing within each burst
OPTIONS
• Clock Cycle Timing
3ns (333 MHz)
3.3ns (300 MHz)
4ns (250 MHz)
5ns (200MHz)
6ns (167 MHz)
7.5ns (133 MHz)
• Configurations
2 Meg x 8
1 Meg x 18
512K x 36
• Package
165-ball, 13mm x 15mm FBGA
MARKING
-3
-3.3
-4
-5
-6
-7.5
MT54W2MH8J
MT54W1MH18J
MT54W512H36J
F
VALID PART NUMBERS
PART NUMBER
MT54W2MH8JF-xx
MT54W1MH18JF-xx
MT54W512H36JF-xx
18Mb 1.8V V
DD
, HSTL, QDRIIb4 SRAM
MT54W1MH18J_3.p65 – Rev. 3, Pub. 12/01
DESCRIPTION
2 Meg x 8, QDRIIb4 FBGA
1 Meg x 18, QDRIIb4 FBGA
512K x 36, QDRIIb4 FBGA
1
©2001, Micron Technology, Inc.
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE
BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
‡
PRODUCTS
ADVANCE
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, QDRIIb4 SRAM
GENERAL DESCRIPTION (continued)
of four is fixed and sequential, beginning with the lowest
address and ending with the highest one. All synchro-
nous data outputs pass through output registers con-
trolled by the rising edges of the output clocks (C and C#
if provided; otherwise, K and K#).
Four pins are used to implement JTAG test capabili-
ties: test mode select (TMS), test data-in (TDI), test clock
(TCK), and test data-out (TDO). JTAG circuitry is used to
serially shift data to and from the SRAM. JTAG inputs use
1.8V I/O levels to shift data during this testing mode of
operation.
The SRAM operates from a +1.8V power supply, and
all inputs and outputs are HSTL-compatible. The device
is ideally suited for applications that benefit from a high-
speed, fully-utilized DDR data bus.
Please refer to Micron’s Web site (www.micron.com/
sram)
for the latest data sheet.
cally controlled so that the bus is released if no data is
being delivered. This permits banked SRAM systems with
no complex OE timing generation. Back-to-back READ
cycles are initiated at every second K rising edge. Any
read request in between is ignored, since the burst
squence may not be interrupted and requires two full
clock cycles.
WRITE cycles are initiated by W# LOW at K rising
edge. Data is expected at both rising edges of K and K#,
beginning one clock period later. Write registers are in-
corporated to facilitate pipelined self-timed WRITE cycles
and provide fully coherent data for all combinations of
reads and writes. A read can immediately follow a write
even if they are to the same address. Although the write
data has not been written to the memory array, the SRAM
will deliver the data from the write register instead of
using the older data from the memory array. The latest
data is always utilized for all bus transactions. WRITE
cycles are initiated every second K rising edge. Any in-
between WRITE request is ignored, since the burst se-
quence may not be interrupted.
READ/WRITE OPERATIONS
All bus transactions operate on an uninterruptable
burst-of-four data, and require two full clock cycles of
bus utilization. Any request that attempts to interrupt a
burst-in-progress is ignored. The resulting benefit is that
the address rate is kept down to the clock frequency even
when both buses are 100 percent utilized.
READ cycles are pipelined. The request is initiated by
asserting R# LOW at K rising edge. Data is delivered after
the next rising edge of K using C and C# as the output
timing references; or using K and K#, if C and C# are tied
HIGH. If C and C# are tied HIGH, they may not be toggled
during device operation. Output tri-stating is automati-
PARTIAL WRITE OPERATIONS
BYTE WRITE operations are supported except for x8
devices, in which nybble write is supported. The active
LOW write controls, BWx# (NWx#), are registered coinci-
dent with their corresponding data. This feature can elimi-
nate the need for some READ-MODIFY-WRITE cycles,
collapsing it to a single BYTE/NYBBLE WRITE operation
in some instances.
FUNCTIONAL BLOCK DIAGRAM
1 MEG x 18
n
n
ADDRESS
REGISTRY
& LOGIC
ADDRESS
R#
W#
K
W#
BW0#
BW1#
D (Data In)
R#
K
K#
36
18
DATA
REGISTRY
& LOGIC
WR
R E
I G
T
E 2
WD
R R
I I
T V
E E
R
2
n
x 72
MEMORY
ARRAY
S
E A
NM
S P
E S
MUX
36
RO
E U 72
G T
P
AU
T
C
MUX
C,C#
or
K,K#
O
U
T
P
U
T
S
E
L
E
C
T
O
U
T
P
U
T
B
U
F
F
E
R
18
36
K
36
Q
(Data Out)
2
CQ, CQ#
(Echo CLock Out)
NOTE:
1. The functional block diagram illustrates simplified device operation. See truth table, pin descriptions, and timing
diagrams for detailed information. The x8 and x36 operation is the same, with appropriate adjustments of depth and
width.
2. n = 18
18Mb 1.8V V
DD
, HSTL, QDRIIb4 SRAM
MT54W1MH18J_3.p65 – Rev. 3, Pub. 12/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
ADVANCE
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, QDRIIb4 SRAM
PROGRAMMABLE IMPEDANCE OUTPUT
BUFFER
The QDR SRAM is equipped with programmable im-
pedance output buffers. This allows a user to match the
driver impedance to the system. To adjust the imped-
ance, an external precision resistor (RQ) is connected
between the ZQ pin and V
SS
. The value of the resistor
must be five times the desired impedance. For example,
a 350W resistor is required for an output impedance of
70W. To ensure that output impedance is one fifth the
value of RQ (within 10 percent), the range of RQ is 175W
to 350W. Alternately, the ZQ pin can be connected di-
rectly to V
DD
, which will place the device in a minimum
impedance mode.
Output impedance updates may be required because,
over time, variations may occur in supply voltage and
temperature. The device samples the value of RQ. An
update of the impedance is transparent to the system.
Impedance updates do not affect device operation, and
all data sheet timing and current specifications are met
during an update.
The device will power up with an output impedance
set at 50W. To guarantee optimum output driver imped-
ance after power-up, the SRAM needs 1,024 cycles to
update the impedance. The user can operate the part
with fewer than 1,024 clock cycles, but optimal output
impedance is not guaranteed.
CLOCK CONSIDERATIONS
This device utilizes internal delay-locked loops for
maximum output, data valid window. It can be placed
into a stopped-clock state to minimize power with a
modest restart time of 1,024 clock cycles. Circuitry auto-
matically resets the DLL when the absence of input clock
is detected. See Micron Technical Note TN-54-02 for
more information on clock DLL start-up procedures.
SINGLE CLOCK MODE
The SRAM can be used with the single K, K# clock pair
by tying C and C# HIGH. In this mode, the SRAM will use
K and K# in place of C and C#. This mode, provides the
most rapid data output but does not compensate for
system clock skew and flight times.
DEPTH EXPANSION
Port select inputs are provided for the read and write
ports. This allows for easy depth expansion. Both port
selects are sampled on the rising edge of K only. Each port
can be independently selected and deselected and does
not affect the operation of the opposite port. All pending
transactions are completed prior to a port deselecting.
Depth expansion requires replicating R# and W# control
signals for each bank if it is desired to have bank indepen-
dent READ and WRITE operations.
APPLICATION EXAMPLE
SRAM #1
Vt
R
D
SA0:n
B
W
R W x
# # #
ZQ
Q
C C# K K#
R = 250Ω
D
SA0:n
SRAM #4
B
W
R W x
# # #
ZQ
Q
C C# K K#
R = 250Ω
DATA IN 0:71
DATA OUT 0:71
Address
Read#
BUS
Write#
MASTER
BW0:7#
R
Vt
Vt
(CPU
or
ASIC)
Source K
Source K#
Delayed K
Delayed K#
R
R = 50Ω Vt = V
REF
/2
NOTE:
In this approach, the second clock pair drives the C and C# clocks, but is delayed such that return data meets data setup
and hold times at the bus master.
18Mb 1.8V V
DD
, HSTL, QDRIIb4 SRAM
MT54W1MH18J_3.p65 – Rev. 3, Pub. 12/01
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
ADVANCE
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, QDRIIb4 SRAM
2 MEG x 8 PIN ASSIGNMENT (TOP VIEW)
165-BALL FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/SA*
NC
NC
D4
NC
NC
D5
V
REF
NC
NC
Q6
NC
D7
NC
TCK
3
SA
NC
NC
NC
Q4
NC
Q5
V
DD
Q
NC
NC
D6
NC
NC
Q7
SA
4
W#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
5
NW1#
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C#
7
NC
NW0#
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
SA
10
V
SS
/SA*
NC
NC
NC
D2
NC
NC
V
REF
Q1
NC
NC
NC
NC
NC
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
*Expansion addresses: 10A for 36Mb, 2A for 72Mb.
NOTE:
NW0# controls writes to D0:D3. NW1# controls writes to D4:D7.
18Mb 1.8V V
DD
, HSTL, QDRIIb4 SRAM
MT54W1MH18J_3.p65 – Rev. 3, Pub. 12/01
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
ADVANCE
2 MEG x 8, 1 MEG x 18, 512K x 36
1.8V V
DD
, HSTL, QDRIIb4 SRAM
1 MEG x 18 PIN ASSIGNMENT (TOP VIEW)
165-BALL FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
/SA*
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
NC/SA*
D9
D10
Q10
Q11
D12
Q13
V
DD
Q
D14
Q14
D15
D16
Q16
Q17
SA
4
W#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
5
BW1#
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K#
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C#
7
NC
BW0#
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R#
SA
V
SS
V
SS
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DD
Q
NC
NC
NC
NC
NC
NC
SA
10
V
SS
/SA*
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
*Expansion addresses: 3A for 36Mb, 10A for 72Mb, 2A for 144Mb.
NOTE:
BW0# controls writes to D0:D8. BW1# controls writes to D9:D17.
18Mb 1.8V V
DD
, HSTL, QDRIIb4 SRAM
MT54W1MH18J_3.p65 – Rev. 3, Pub. 12/01
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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