Clock Switch for ATCA/AMC and PCIe
Applications
Data Sheet
831752
General Description
The 831752 is a high-performance, differential HCSL clock switch.
The device is designed for the routing of PCIe clock signals in
ATCA/AMC system and is optimized for PCIe Gen 1, Gen 2 and Gen
3. The device has one differential, bi-directional I/O (FCLK) for
connection to ATCA clock sources and to clock receivers through a
connector. The differential clock input CLK is the local clock input
and the HCSL output Q is the local clock output. In the common
clock mode, FCLK serves as an input and is routed to the differential
HCSL output Q. There are two local clock modes. In the local clock
mode 0, CLK is the input, Q is the clock output and FCLK is in
high-impedance state. In the local clock mode 1, CLK is the input
and both Q and FCLK are the outputs of the locally generated PCIe
clock signal. The 831752 is characterized to operate from a 3.3V
power or 2.5V power supply. The 831752 supports the switching of
PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) clock
signals.
Features
•
Clock switch for PCIe and ATCA/AMC applications
•
Supports local and common ATCA/AMC clock modes
•
Bi-directional clock I/O FCLK:
•
•
•
•
•
•
•
•
•
Pin Assignment
DIR_SEL
nOEFCLK
VDD
FCLK
nFCLK
GND
CLK
nCLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IREF
GND
VDD
Q
nQ
GND
VDD
nc
- When operating as an output, FCLK is a source-terminated
HCSL signal.
- When operating as an input, FCLK accepts HCSL, LVDS and
LVPECL levels.
Local clock input (CLK) accepts HCSL, LVDS and LVPECL
differential signals
Local HCSL clock output (Q)
Maximum input/output clock frequency: 500MHz
Maximum input/output data rate: 1000Mb/s (NRZ)
LVCMOS interface levels for the control inputs
PCI Express (2.5 Gb/S), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) jitter
compliant
Full 3.3V or 2.5V supply voltage
Lead-free (RoHS 6) 16-lead TSSOP package
-40°C to 85°C ambient operating temperature
831752
16-lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package, Top View
Block Diagram
FCLK
nFCLK
50
50
1
22.33
22.33
1=disable
0
50
50
Q
nQ
CLK
nCLK
nOEFCLK
DIR_SEL
IREF
Pulldown
Pullup/Pulldown
Pullup
Pulldown
©2016 Integrated Device Technology, Inc
1
Revision B June 28, 2016
831752 Data Sheet
Table 1. Pin Descriptions
Number
1
2
3, 10, 14
Name
DIR_SEL
nOEFCLK
V
DD
Input
Input
Power
Type
Pulldown
Pullup
Description
Direction control for the FCLK I/O. Works in conjunction with nOEFCLK.
See Table 3 for function. LVCMOS/LVTTL interface levels.
Output enable for the FCLK I/O output. Works in conjunction with
DIR_SEL. See Table 3 for function. LVCMOS/LVTTL interface levels.
Core and output power supply pin.
Differential I/O. Signal direction is controlled by DIR_SEL. Accepts
differential signals when operating as an input. Differential HCSL
signals when operating as an output. Internal source termination can be
disabled. See Table 3 for function.
Power supply ground.
Pulldown
Pulldown/Pullup
Non-inverting input.
Inverting differential clock input.
No connect.
Differential output pair. HCSL interface levels.
An external fixed precision resistor (475
) from this pin to ground
provides a reference current used for the differential current-mode Q
and FCLK outputs.
4, 5
FCLK, nFCLK
I/O
6, 11, 15
7
8
9
12, 13
16
GND
CLK
nCLK
nc
nQ, Q
IREF
Power
Input
Input
Unused
Output
Input
NOTE: Pullup
and pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Table
Table 3. Direction Control Function Table
Input
DIR_SEL
0
0 (default)
Input
nOEFCLK
0
1 (default)
Operation
Local clock mode 0. The input signal at CLK is routed to
both outputs Q and FCLK.
Local clock mode 1. The input signal at CLK is routed to
the output Q.
Common reference clock mode. FCLK is the clock input.
Q is the clock output.
FCLK Function
Differential HCSL output with internal 50 source
termination
Output is disabled (high impedance). Internal 50
termination is disabled.
Differential clock input. Internal 50 source
termination is disabled as well as output driver and
22.33
resistors.
1
X
NOTE: X = 0 or 1
©2016 Integrated Device Technology, Inc
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Revision B June 28, 2016
831752 Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
81.2°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Core Supply Voltage
2.375
Power Supply Current
2.5
2.625
64
V
mA
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
Input Low Voltage
DIR_SEL
I
IH
Input High Current
nOEFLCK
DIR_SEL
I
IL
Input Low Current
nOEFLCK
V
DD
= 2.625V or 3.465V, V
IN
= 0V
V
DD
= V
IN
= 2.625V or 3.465V
-5
-150
V
DD
= 3.3V
V
DD
= 2.5V
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
V
IL
Table 4C. Differential DC Characteristics, V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input
High Current
Input
Low Current
CLK, nCLK
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.3V
V
DD
= 3.3V, V
IN
= 0V
V
DD
= 3.3V, V
IN
= 0V
-5
-150
0.15
0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
©2016 Integrated Device Technology, Inc
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Revision B June 28, 2016
831752 Data Sheet
AC Electrical Characteristics
Table 5A. PCI Express Jitter Specifications, V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
t
j
(PCIe Gen 1)
Parameter
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
Test Conditions
ƒ = 100MHz
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ = 100MHz
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ = 100MHz
Low Band: 10kHz - 1.5MHz
ƒ = 100MHz
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
Minimum
Typical
9.95
Maximum
15.5
PCIe Industry
Specification
86
Units
ps
t
REFCLK_HF_RMS
Phase Jitter RMS;
NOTE 2, 4
(PCIe Gen 2)
t
REFCLK_LF_RMS
(PCIe Gen 2)
t
REFCLK_RMS
(PCIe Gen 3)
Phase Jitter RMS;
NOTE 2, 4
Phase Jitter RMS;
NOTE 3, 4
0.82
1.12
3.1
ps
0.04
0.08
3.0
ps
0.153
0.203
0.8
ps
NOTE:
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the
PCI Express Application Note section
in the datasheet.
NOTE: PCI
Express Jitter Specifications apply to FCLK and nFCLK and Q, nQ operating as outputs. The source generator used in the PCI
Express Jitter measurements is the Stanford Research Systems CG635 2.0GHz Synthesized Clock Generator.
NOTE 1:
Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express
Gen 1 is 86ps peak-to-peak for a sample size of 10
6
clock periods.
NOTE 2:
RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Gen 2 is 3.1ps RMS for t
REFCLK_HF_RMS
(High Band)
and 3.0ps RMS for t
REFCLK_LF_RMS
(Low Band).
NOTE 3:
RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the
PCI Express
Base Specification Revision 0.7, October 2009
and is subject to change pending the final release version of the specification.
NOTE 4:
This parameter is guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc
4
Revision B June 28, 2016
831752 Data Sheet
Table 5B. HCSL AC Characteristics, V
DD
= 3.3V±5% or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
f
OUT
tjit
Parameter
Output Frequency
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Plot
100MHz, Integration Range:
12kHz – 20MHz
FCLK to Q
t
PD
Propagation Delay, NOTE 1
CLK to Q
CLK to FCLK
MUX
ISOL
Edge Rate
V
RB
t
STABLE
V
MAX
V
MIN
V
CROSS
V
CROSS
odc
Mux Isolation
Rise/Fall Edge Rate; NOTE 2, 3
Ringback Voltage; NOTE 2, 4
Time before V
RB
is allowed;
NOTE 2, 4
Absolute Max Output Voltage;
NOTE 5, 6
Absolute Min Output Voltage;
NOTE 5, 7
Absolute Crossing Voltage;
NOTE 5, 8, 9
Total Variation of V
CROSS
over all
edges; NOTE 5, 8, 10
f
312.5MHz
Output Duty Cycle; NOTE 11
f > 312.5MHz
40
50
60
44
-300
250
f = 100MHz
0.6
-100
500
800
-35
385
40
50
650
140
56
1350
1.75
1.95
1.50
-70
4
100
Test Conditions
Minimum
Typical
100
0.3
Maximum
500
0.505
3.65
3.90
3.70
Units
MHz
ps
ns
ns
ns
dB
V/ns
mV
ps
mV
mV
mV
mV
%
NOTE:
Measurements taken with Q output and FCLK output.
NOTE:
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE:
All measurements were taken with FCLK, nFCLK and Q, nQ operating as outputs unless otherwise noted.
NOTE 1:
Measured from the differential input cross point to the differential output crossing point.
NOTE 2:
Measurement taken from differential waveform.
NOTE 3:
Measurement from -150mV to +150mV on the differential waveform (derived from Q minus nQ). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 4:
T
STABLE
is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the V
RB
±100 differential range. See Parameter Measurement Information Section.
NOTE 5:
Measurement taken from single-ended waveform.
NOTE 6:
Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 7:
Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 8:
Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.
See Parameter Measurement Information Section.
NOTE 9:
Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 10:
Defined as the total variation of all crossing voltage of rising Q and falling nQ. This is the maximum allowed variance in the V
CROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 11:
Input duty cycle must be 50%.
NOTE 12:
Matching applies to rising edge rate for Q and falling edge rate for nQ. It is measured using a ±75mV window centered on the
median crosspoint where Q meets nQ falling. The median crosspoint is used to calculate the voltage thresholds the oscilloscope is to use for
the edge rate calculations. The rise edge rate of Q should be compared to the fall edge rate of nQ, the maximum allowed difference should not
exceed 20% of the slowest edge rate.
©2016 Integrated Device Technology, Inc
5
Revision B June 28, 2016
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