Blackfin
Embedded Processor
ADSP-BF531/ADSP-BF532/ADSP-BF533
FEATURES
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of pro-
gramming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Wide range of operating voltages (see
Operating Conditions
on Page 20)
Qualified for Automotive Applications (see
Automotive Prod-
ucts on Page 62)
Programmable on-chip voltage regulator
160-ball CSP_BGA, 169-ball PBGA, and 176-lead LQFP
packages
PERIPHERALS
Parallel peripheral interface PPI, supporting
ITU-R 656 video data formats
2 dual-channel, full duplex synchronous serial ports, sup-
porting eight stereo I
2
S channels
2 memory-to-memory DMAs
8 peripheral DMAs
SPI-compatible port
Three 32-bit timer/counters with PWM support
Real-time clock and watchdog timer
32-bit core timer
Up to 16 general-purpose I/O pins (GPIO)
UART with support for IrDA
Event handler
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
MEMORY
Up to 148K bytes of on-chip memory (see
Table 1 on Page 3)
Memory management unit providing memory protection
External memory controller with glueless support for
SDRAM, SRAM, flash, and ROM
Flexible memory booting options from SPI and
external memory
VOLTAGE REGULATOR
JTAG TEST AND EMULATION
B
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
INTERRUPT
CONTROLLER
PERIPHERAL ACCESS BUS
WATCHDOG
TIMER
RTC
PPI
DMA
CONTROLLER
DMA ACCESS BUS
TIMER0
-
2
SPI
UART
SPORT0
-
1
DMA CORE BUS
EXTERNAL ACCESS BUS
DMA
EXTERNAL
BUS
GPIO
PORT
F
EXTERNAL PORT
FLASH, SDRAM CONTROL
16
BOOT ROM
Figure 1. Functional Block Diagram
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Rev. I
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ADSP-BF531/ADSP-BF532/ADSP-BF533
TABLE OF CONTENTS
Features ................................................................. 1
Memory ................................................................ 1
Peripherals ............................................................. 1
General Description ................................................. 3
Portable Low Power Architecture ............................. 3
System Integration ................................................ 3
Processor Peripherals ............................................. 3
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 4
DMA Controllers .................................................. 8
Real-Time Clock ................................................... 8
Watchdog Timer .................................................. 9
Timers ............................................................... 9
Serial Ports (SPORTs) ............................................ 9
Serial Peripheral Interface (SPI) Port ....................... 10
UART Port ........................................................ 10
General-Purpose I/O Port F ................................... 10
Parallel Peripheral Interface ................................... 11
Dynamic Power Management ................................ 11
Voltage Regulation .............................................. 13
Clock Signals ..................................................... 13
Booting Modes ................................................... 14
Instruction Set Description ................................... 15
Development Tools .............................................. 15
Additional Information ........................................ 16
Related Signal Chains ........................................... 16
Pin Descriptions .................................................... 17
Specifications ........................................................ 20
Operating Conditions ........................................... 20
Electrical Characteristics ....................................... 22
Absolute Maximum Ratings ................................... 25
ESD Sensitivity ................................................... 25
Package Information ............................................ 26
Timing Specifications ........................................... 27
Output Drive Currents ......................................... 43
Test Conditions .................................................. 45
Thermal Characteristics ........................................ 49
160-Ball CSP_BGA Ball Assignment ........................... 50
169-Ball PBGA Ball Assignment ................................. 53
176-Lead LQFP Pinout ............................................ 56
Outline Dimensions ................................................ 58
Surface-Mount Design .......................................... 61
Automotive Products .............................................. 62
Ordering Guide ..................................................... 63
REVISION HISTORY
8/13— Rev. H to Rev. I
Updated
Development Tools .................................... 15
Corrected Conditions value of the V
IL
specification in
Operating Conditions ............................................. 20
Added notes to Table 30 in
Serial Ports—Enable and Three-State .......................... 36
Added
Timer Clock Timing ...................................... 41
Revised
Timer Cycle Timing ..................................... 41
Updated
Ordering Guide ......................................... 63
Rev. I
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ADSP-BF531/ADSP-BF532/ADSP-BF533
GENERAL DESCRIPTION
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are
members of the Blackfin
®
family of products, incorporating the
Analog Devices, Inc./Intel Micro Signal Architecture (MSA).
Blackfin processors combine a dual-MAC state-of-the-art signal
processing engine, the advantages of a clean, orthogonal RISC-
like microprocessor instruction set, and single instruction, mul-
tiple data (SIMD) multimedia capabilities into a single
instruction set architecture.
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are
completely code and pin-compatible, differing only with respect
to their performance and on-chip memory. Specific perfor-
mance and memory configurations are shown in
Table 1.
Table 1. Processor Comparison
ADSP-BF531
ADSP-BF532
ADSP-BF533
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature
dynamic power management—the ability to vary both the volt-
age and frequency of operation to significantly lower overall
power consumption. Varying the voltage and frequency can
result in a substantial reduction in power consumption, com-
pared with just varying the frequency of operation. This
translates into longer battery life for portable appliances.
SYSTEM INTEGRATION
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors are
highly integrated system-on-a-chip solutions for the next gener-
ation of digital communication and consumer multimedia
applications. By combining industry-standard interfaces with a
high performance signal processing core, users can develop
cost-effective solutions quickly without the need for costly
external components. The system peripherals include a UART
port, an SPI port, two serial ports (SPORTs), four general-pur-
pose timers (three with PWM capability), a real-time clock, a
watchdog timer, and a parallel peripheral interface.
Features
SPORTs
UART
SPI
GP Timers
Watchdog Timers
RTC
Parallel Peripheral Interface
GPIOs
L1 Instruction SRAM/Cache
L1 Instruction SRAM
L1 Data SRAM/Cache
L1 Data SRAM
L1 Scratchpad
L3 Boot ROM
Memory Configuration
Maximum Speed Grade
Package Options:
CSP_BGA
Plastic BGA
LQFP
2
1
1
3
1
1
1
16
16K bytes
16K bytes
16K bytes
4K bytes
1K bytes
2
1
1
3
1
1
1
16
16K bytes
32K bytes
32K bytes
2
1
1
3
1
1
1
16
16K bytes
64K bytes
32K bytes
32K bytes
4K bytes 4K bytes
1K bytes 1K bytes
PROCESSOR PERIPHERALS
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors con-
tain a rich set of peripherals connected to the core via several
high bandwidth buses, providing flexibility in system configura-
tion as well as excellent overall system performance (see the
functional block diagram in
Figure 1 on Page 1).
The general-
purpose peripherals include functions such as UART, timers
with PWM (pulse-width modulation) and pulse measurement
capability, general-purpose I/O pins, a real-time clock, and a
watchdog timer. This set of functions satisfies a wide variety of
typical system support needs and is augmented by the system
expansion capabilities of the part. In addition to these general-
purpose peripherals, the processors contain high speed serial
and parallel ports for interfacing to a variety of audio, video, and
modem codec functions; an interrupt controller for flexible
management of interrupts from the on-chip peripherals or
external sources; and power management control functions to
tailor the performance and power characteristics of the proces-
sor and system to many application scenarios.
All of the peripherals, except for general-purpose I/O, real-time
clock, and timers, are supported by a flexible DMA structure.
There is also a separate memory DMA channel dedicated to
data transfers between the processor’s various memory spaces,
including external SDRAM and asynchronous memory. Multi-
ple on-chip buses running at up to 133 MHz provide enough
bandwidth to keep the processor core running along with activ-
ity on all of the on-chip and external peripherals.
The processors include an on-chip voltage regulator in support
of the processor’s dynamic power management capability. The
voltage regulator provides a range of core voltage levels from
V
DDEXT
. The voltage regulator can be bypassed at the user’s
discretion.
400 MHz 400 MHz 600 MHz
160-Ball 160-Ball 160-Ball
169-Ball 169-Ball 169-Ball
176-Lead 176-Lead 176-Lead
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.
Rev. I
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ADSP-BF531/ADSP-BF532/ADSP-BF533
BLACKFIN PROCESSOR CORE
As shown in
Figure 2 on Page 5,
the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-
tation units process 8-bit, 16-bit, or 32-bit data from the
register file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and
population count, modulo 2
32
multiply, divide primitives, satu-
ration and rounding, and sign/exponent detection. The set of
video instructions includes byte alignment and packing opera-
tions, 16-bit and 8-bit adds with clipping, 8-bit average
operations, and 8-bit subtract/absolute value/accumulate (SAA)
operations. Also provided are the compare/select and vector
search instructions.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). Quad 16-bit operations
are possible using the second ALU.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
MEMORY ARCHITECTURE
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors view
memory as a single unified 4G byte address space, using 32-bit
addresses. All resources, including internal memory, external
memory, and I/O control registers, occupy separate sections of
this common address space. The memory portions of this
address space are arranged in a hierarchical structure to provide
a good cost/performance balance of some very fast, low latency
on-chip memory as cache or SRAM, and larger, lower cost and
performance off-chip memory systems. See
Figure 3, Figure 4,
and
Figure 5 on Page 6.
The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the external bus interface unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132M bytes of
physical memory.
The memory DMA controller provides high bandwidth data-
movement capability. It can perform block transfers of code or
data between the internal memory and the external
memory spaces.
Internal (On-Chip) Memory
The processors have three blocks of on-chip memory that pro-
vide high bandwidth access to the core.
The first block is the L1 instruction memory, consisting of up to
80K bytes SRAM, of which 16K bytes can be configured as a
four way set-associative cache. This memory is accessed at full
processor speed.
Rev. I
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August 2013
ADSP-BF531/ADSP-BF532/ADSP-BF533
ADDRESS ARITHMETIC UNIT
I3
I2
I1
I0
DA1 32
DA0 32
TO MEMORY
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG1
DAG0
SP
FP
P5
P4
P3
P2
P1
P0
32
RAB
32
PREG
SD 32
LD1 32
LD0 32
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
32
32
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
BARREL
SHIFTER
40
A0
32
40
40
40
A1
8
16
8
8
16
ASTAT
SEQUENCER
ALIGN
8
DECODE
LOOP BUFFER
CONTROL
UNIT
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
The second on-chip memory block is the L1 data memory, con-
sisting of one or two banks of up to 32K bytes. The memory
banks are configurable, offering both cache and SRAM func-
tionality. This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM, which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
1M byte segment regardless of the size of the devices used, so
that these banks are only contiguous if each is fully populated
with 1M byte of memory.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space.
On-chip I/O devices have their control registers mapped into
memory mapped registers (MMRs) at addresses near the top of
the 4G byte address space. These are separated into two smaller
blocks, one containing the control MMRs for all core functions,
and the other containing the registers needed for setup and con-
trol of the on-chip peripherals outside of the core. The MMRs
are accessible only in supervisor mode and appear as reserved
space to on-chip peripherals.
External (Off-Chip) Memory
External memory is accessed via the external bus interface unit
(EBIU). This 16-bit interface provides a glueless connection to a
bank of synchronous DRAM (SDRAM) as well as up to four
banks of asynchronous memory devices including flash,
EPROM, ROM, SRAM, and memory mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed
to interface to up to 128M bytes of SDRAM. The SDRAM con-
troller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.
The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
Booting
The ADSP-BF531/ADSP-BF532/ADSP-BF533 processors con-
tain a small boot kernel, which configures the appropriate
peripheral for booting. If the processors are configured to boot
from boot ROM memory space, the processor starts executing
from the on-chip boot ROM. For more information, see
Boot-
ing Modes on Page 14.
Rev. I
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August 2013
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