Low Skew, 1-to-10,
Differential-to-2.5V, 3.3V LVPECL/ECL
853S111B
Datasheet
Description
The 853S111B is a low skew, high performance 1-to-10
Differential-to-2.5V/ 3.3V LVPECL/ECL Fanout Buffer. The
853S111B is characterized to operate from either a 2.5V or a 3.3V
power supply.
Guaranteed output and part-to-part skew characteristics make the
853S111B ideal for those clock distribution applications demanding
well defined performance and repeatability.
Features
•
•
•
•
•
•
•
•
•
•
Ten differential 2.5V, 3.3V LVPECL/ECL outputs
Two selectable differential input pairs
PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, SSTL, CML
Maximum output frequency: 2.5GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Output skew: 50ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 645ps (maximum)
Additive Phase Jitter, RMS: 0.03ps (typical)
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3.8V to -2.375V
-40°C to 85°C ambient operating temperature
Available lead-free (RoHS 6) packaging
Supports
105°C board temperature operations
Pin Assignments
Q4
nQ6
nQ3
nQ4
nQ5
Q3
Q5
Q6
•
•
•
•
24 23 22 21 20 19 18
V
CCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
CCO
25
26
27
17
16
V
CCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
V
CCO
853S111B
15
14
32-Lead TQFP, E-Pad
28
7mm x 7mm x 1
mm
13
29
12
package body
30
Y Package
11
Top View
31
10
32
1
V
CC
Block Diagram
PCLK0
Pulldown
nPCLK0
Pullup/Pulldown
PCLK1
Pulldown
nPCLK1
Pullup/Pulldown
CLK_SEL
Pulldown
V
BB
1
Q1
nQ1
Q2
nQ2
nQ3
nQ3
Q4
0
Q0
nQ0
9
2
CLK_SEL
3
PCLK0
4
nPCLK0
5
V
BB
6
PCLK1
7
nPCLK1
Q6
8
V
EE
24 23 22 21 20 19 18
V
CCO
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
CCO
25
26
27
Q4
nQ5
Q5
17
16
V
CCO
Q7
nQ7
Q8
nQ6
nQ3
nQ4
Q3
nQ4
Q5
nQ5
Q6
853S111B
15
14
13
12
11
10
9
32-Lead VFQFN
5mm x 5mm x 0.925
mm
29
package body
30
K Package
Top View
31
28
32
1
V
CC
nQ8
nQ6
Q9
nQ9
V
CCO
Q7
nQ7
nQ8
nQ8
Q9
nQ9
2
CLK_SEL
3
PCLK0
4
nPCLK0
5
V
BB
6
PCLK1
7
nPCLK1
8
V
EE
©2017 Integrated Device Technology, Inc.
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September 8, 2017
853S111B Datasheet
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23, 24
26, 27
28, 29
30, 31
Name
V
CC
CLK_SEL
PCLK0
nPCLK0
V
BB
PCLK1
nPCLK1
V
EE
V
CCO
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Power
Input
Input
Input
Output
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Positive supply pin.
Clock select input. When HIGH, selects PCLK1/nPCLK1 inputs. When
LOW, selects PCLK0/nPCLK0 inputs. LVPECL interface levels. Also
accepts standard LVCMOS input levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Bias voltage to be connected for single-ended applications.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
CC
/2 default when left floating.
Negative supply pin.
Output supply pins.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
Differential output pair. LVPECL/ECL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
R
PULLDOWN
R
VCC/2
Parameter
Input Pulldown Resistor
RPullup/Pulldown Resistors
Test Conditions
Minimum
Typical
75
50
Maximum
Units
k
k
©2017 Integrated Device Technology, Inc.
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September 8, 2017
853S111B Datasheet
Function Tables
Table 3A. Clock Input Function Table
Inputs
PCLK0 or PCLK1
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nPCLK0 or nPCLK1
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q0:Q9
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ0:nQ9
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Please refer to the Applications Information, “Wiring the Differential Input to Accept Single Ended Levels”.
Table 3B. Control Input Function Table
Inputs
CLK_SEL
0
1
Selected Source
PCLK0, nPCLK0
PCLK1, nPCLK1
©2017 Integrated Device Technology, Inc.
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September 8, 2017
853S111B Datasheet
Absolute Maximum Ratings
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
V
BB
Sink//Source, I
BB
Operating Temperature Range, T
A
Package Thermal Impedance,
JA
32-Lead TQFP, ePad
32_Lead VFQFN
Storage Temperature, T
STG
Rating
4.6V (LVPECL mode, V
EE
= 0V)
-4.6V (ECL mode, V
CC
= 0V)
-0.5V to V
CC
+ 0.5V
0.5V to V
EE
– 0.5V
50mA
100mA
±0.5mA
-40C to +85C
36.2C/W (0 mps)
42.7C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= V
CCO
= 2.375V to 3.8V; V
EE
= 0V, T
A
= -40°C to 85°C, T
B
= -40°C to 105°C
Symbol
V
CC
V
CCO
I
EE
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
3.3
3.3
Maximum
3.8
3.8
124
Units
V
V
mA
©2017 Integrated Device Technology, Inc.
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September 8, 2017
853S111B Datasheet
Table 4B. LVPECL DC Characteristics,
V
CC
= V
CCO
= 3.3V; V
EE
= 0V, T
A
= -40°C to 85°C, T
B
= -40°C to 105°C
-40°C
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR1
V
CMR2
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage (Single-ended)
Input Low Voltage (Single-ended)
Output Voltage Reference;
NOTE 2
Peak-to-Peak Input Voltage;
NOTE 3
Input High Voltage Common Mode
Range; NOTE 3, 4
Input Voltage Common Mode Range
referenced to Cross-point; NOTE 3,
5
Input
High Current
Input
Low Current
PCLK0, PCLK1
nPCLK0, nPCLK1
PCLK0, PCLK1
nPCLK0, nPCLK1
-10
-200
Min
2.175
1.405
2.075
1.43
1.86
150
1.3
1.3 -
V
PP
/2
800
Typ
2.275
1.545
Max
2.445
1.70
2.36
1.765
1.98
1300
3.3
3.3 -
V
PP
/2
200
-10
-200
Min
2.225
1.375
2.075
1.43
1.86
150
1.2
1.2 -
V
PP
/2
800
25°C
Typ
2.295
1.52
Max
2.445
1.645
2.36
1.765
1.98
1200
3.3
3.3 -
V
PP
/2
200
-10
-200
Min
2.215
1.355
2.075
1.43
1.86
150
1.2
1.2 -
V
PP
/2
800
85°C
Typ
2.33
1.535
Max
2.410
1.63
2.36
1.765
1.98
1200
3.3
3.3 -
V
PP
/2
200
Units
V
V
V
V
V
mV
V
V
µA
µA
µA
NOTE: Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50 to V
CCO
– 2V.
NOTE 2: Single-ended input operation is limited. V
CC
3V in LVPECL mode.
NOTE 3: V
IL
should not be less than V
EE
– 0.3V, V
IH
should not be greater than V
CC
.
NOTE 4: Common mode voltage is defined as V
IH
.
NOTE 5: Common mode voltage is defined as V
CROSS-POINT
.
©2017 Integrated Device Technology, Inc.
5
September 8, 2017
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