NLAS4053
Analog Multiplexer/
Demultiplexer
Triple 2:1 Analog Switch−Multiplexer
Improved Process, Sub−Micron Silicon
Gate CMOS
The NLAS4053 is an improved version of the MC14053 and
MC74HC4053 fabricated in sub−micron Silicon Gate CMOS
technology for lower R
DS(on)
resistance and improved linearity with
low current. This device may be operated either with a single supply or
dual supply up to
±3.0
V to pass a 6 V
PP
signal without coupling
capacitors.
When operating in single supply mode, it is only necessary to tie
V
EE
, pin 7 to ground. For dual supply operation, V
EE
is tied to a
negative voltage, not to exceed maximum ratings. Pin for pin
compatible with all industry standard versions of ‘4053.’
Features
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MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
1
NLAS4053G
AWLYWW
16
TSSOP−16
DT SUFFIX
CASE 948F
1
A
= Assembly Location
L, WL
= Wafer Lot
Y
= Year
W, WW = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
NLAS
4053
ALYWG
G
•
Improved R
DS(on)
Specifications
•
Pin for Pin Replacement for MAX4053 and MAX4053A
−
One Half the Resistance Operating at 5.0 Volts
•
Single or Dual Supply Operation
−
Single 3−5 Volt Operation, or Dual
±3.0
Volt Operation
−
With V
CC
of 3.0 to 3.3 V, Device Can Interface with 1.8 V Logic,
−
No Translators Needed
−
Address and Inhibit Pins are Over−Voltage Tolerant and May Be
−
Driven Up +6.0 V Regardless of V
CC
−
Greatly Improved Noise Margin Over MAX4053 and MAX4053A
•
Improved Linearity Over Standard HC4053 Devices
•
Popular SOIC and the Space Saving TSSOP Packages
•
Pb−Free Packages are Available*
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2011
March, 2011
−
Rev. 3
1
Publication Order Number:
NLAS4053/D
NLAS4053
NO
B
V
CC
16
COM
B
COM
C
15
14
NO
C
13
NC
C
12
Add
C
11
Add
B
10
Add
A
9
NC
B
NO
A
COM
A
NC
A
1
NO
B
2
NC
B
3
NO
A
4
5
6
7
V
EE
8
GND
Enable
C
B
A
COM
B
COM
C
NO
C
NC
C
COM
A
NC
A
Inhibit
Figure 1. Pin Connection
(Top View)
Figure 2. Logic Diagram
TRUTH TABLE
Address
Inhibit
1
0
C
X
don’t care
0
B
X
don’t care
0
A
X
don’t care
0
ON SWITCHES*
All switches open
COM
A
−NC
A
,
COM
B
−NC
B
,
COM
C
−NC
C
COM
A
−NO
A
,
COM
B
−NC
B
,
COM
C
−NC
C
COM
A
−NC
A
,
COM
B
−NO
B
,
COM
C
−NC
C
COM
A
−NO
A
,
COM
B
−NO
B
,
COM
C
−NC
C
COM
A
−NC
A
,
COM
B
−NC
B
,
COM
C
−NO
C
COM
A
−NO
A
,
COM
B
−NC
B
,
COM
C
−NO
C
COM
A
−NC
A
,
COM
B
−NO
B
,
COM
C
−NO
C
COM
A
−NO
A
,
COM
B
−NO
B
,
COM
C
−NO
C
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
*NO, NC, and COM pins are identical and interchangeable. Either may be
considered an input or output; signals pass equally well in either direction.
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2
NLAS4053
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MAXIMUM RATINGS
Symbol
V
EE
Parameter
Value
Unit
V
V
V
V
Negative DC Supply Voltage
(Referenced to GND)
(Referenced to GND)
(Referenced to V
EE
)
−7.0
to
)0.5
−0.5
to
)7.0
−0.5
to
)7.0
V
CC
V
IS
I
Positive DC Supply Voltage (Note 1)
Analog Input Voltage
Digital Input Voltage
V
EE
−0.5
to V
CC
)0.5
−0.5
to 7.0
$50
V
IN
(Referenced to GND)
DC Current, Into or Out of Any Pin
Storage Temperature Range
mA
_C
_C
_C
T
STG
T
L
T
J
−65
to
)150
260
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
)150
143
164
500
450
q
JA
P
D
SOIC
TSSOP
SOIC
TSSOP
°C/W
mW
Power Dissipation in Still Air,
Moisture Sensitivity
MSL
F
R
Level 1
Flammability Rating
Oxygen Index: 30%
−
35%
UL 94 V−0 @ 0.125 in
u2000
u200
u1000
$300
V
ESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
V
I
LATCHUP
Latchup Performance
Above V
CC
and Below GND at 125°C (Note 5)
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The absolute value of V
CC
$
|V
EE
|
≤
7.0.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
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V
EE
Negative DC Supply Voltage
Positive DC Supply Voltage
Analog Input Voltage
Digital Input Voltage
(Referenced to GND)
(Referenced to GND)
(Referenced to V
EE
)
−5.5
2.5
2.5
GND
5.5
6.6
V
V
V
V
V
CC
V
IS
T
A
V
EE
0
−55
0
0
V
CC
5.5
125
100
20
V
IN
(Note 6) (Referenced to GND)
Operating Temperature Range, All Package Types
_C
t
r
, t
f
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
CC
= 3.0 V
$
0.3 V
V
CC
= 5.0 V
$
0.5 V
ns/V
6. Unused digital inputs may not be left open. All digital inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
Symbol
Parameter
Min
Max
Unit
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3
NLAS4053
ORDERING INFORMATION
Device
NLAS4053DG
NLAS4053DR2
NLAS4053DR2G
NLAS4053DT
NLAS4053DTG
NLAS4053DTR2
NLAS4053DTR2G
Package
SOIC−16
(Pb−Free)
SOIC−16
SOIC−16
(Pb−Free)
TSSOP−16*
TSSOP−16*
TSSOP−16*
TSSOP−16*
Shipping
†
48 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
96 Units / Rail
96 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
DC CHARACTERISTICS
−
Digital Section
(Voltages Referenced to GND)
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage, Address and Inhibit Inputs
Condition
V
CC
V
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
V
IN
= 6.0 or GND
Channel Select, Enable and
V
IS
= V
CC
or GND
0 V to 6.0 V
6.0
Guaranteed Limit
−55
to 25°C
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
$0.1
4.0
v85°C
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
$1.0
40
v125°C
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
$1.0
80
Unit
V
V
IL
Maximum Low−Level Input
Voltage, Address and Inhibit Inputs
V
I
IN
I
CC
Maximum Input Leakage Current,
Address or Inhibit Inputs
Maximum Quiescent Supply
Current (per Package)
mA
mA
DC ELECTRICAL CHARACTERISTICS
−
Analog Section
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î
Symbol
R
ON
Parameter
Test Conditions
V
CC
V
3.0
4.5
3.0
3.0
4.5
3.0
V
EE
V
−55
to 25°C
86
37
26
15
13
10
4
2
v85_C
108
46
33
20
18
15
4
2
v125_C
120
55
37
20
18
15
5
3
Unit
W
Maximum “ON” Resistance
V
IN
= V
IL
or V
IH
V
IS
= V
EE
to V
CC
|I
S
| = 10 mA
(Figures 4 thru 9)
V
IN
= V
IL
or V
IH,
|I
S
| = 10 mA,
0
0
−3.0
0
0
−3.0
0
−3.0
0
−3.0
DR
ON
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
IS
= 2.0 V
V
IS
= 3.5 V
V
IS
= 2.0 V
W
R
flat(ON)
COM−NO
On−Resistance Flatness
V
com
1, 2, 3.5 V
V
com
−2,
0, 2 V
|I
S
| = 10 mA
4.5
3.0
W
I
NC(OFF)
I
NO(OFF)
I
COM(ON)
Maximum Off−Channel Leakage
Current
Switch Off
V
IN
= V
IL
or V
IH
V
IO
= V
CC
−1.0
V or V
EE
+1.0 V
(Figure 17)
Switch On
V
IO
= V
CC
−1.0
V or V
EE
+1.0 V
(Figure 17)
6.0
3.0
0.1
0.1
5.0
5.0
100
100
nA
Maximum On−Channel Leakage
Current, Channel− to−Channel
6.0
3.0
0
−3.0
0.1
0.1
5.0
5.0
100
100
nA
Guaranteed Limit
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4
NLAS4053
AC CHARACTERISTICS
(Input t
r
= t
f
= 3 ns)
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ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ
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Î
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Î Î ÎÎÎÎÎÎ ÎÎ
Î
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Î
Î ÎÎ
Î
Î
Guaranteed Limit
Typ*
6.5
5.0
3.5
Symbol
t
BBM
Parameter
Test Conditions
V
CC
V
3.0
4.5
3.0
V
EE
V
−55
to 25_C
Min
1.0
1.0
1.0
v85_C
−
−
−
v125_C
−
−
−
Unit
ns
Minimum Break−Before−Make
Time
V
IN
= V
IL
or V
IH
V
IS
= V
CC
R
L
= 300
W,
C
L
= 35 pF
(Figure 19)
0.0
0.0
−3.0
*Typical Characteristics are at 25_C.
AC CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 3 ns)
Guaranteed Limit
Symbol
t
TRANS
Parameter
Transition Time
(Address Selection Time)
(Figure 18)
Turn−on Time
(Figures 14, 15, 20, and 21)
Enable to N
O
or N
C
Turn−off Time
(Figures 14, 15, 20, and 21)
Enable to N
O
or N
C
V
CC
V
2.5
3.0
4.5
3.0
2.5
3.0
4.5
3.0
2.5
3.0
4.5
3.0
V
EE
V
0
0
0
−3.0
0
0
0
−3.0
0
0
0
−3.0
−55
to 25°C
Min
Typ
Max
40
28
23
23
40
28
23
23
40
28
23
23
v85°C
Min
Max
45
30
25
25
45
30
25
25
45
30
25
25
Typical @ 25°C, V
CC
= 5.0 V
C
IN
C
NO
or
C
NC
C
COM
C
(ON)
Maximum Input Capacitance,Select Inputs
Analog I/O
Common I/O
Feedthrough
8
10
10
1.0
pF
v125°C
Min
Max
50
35
30
28
50
35
30
28
50
35
30
28
Unit
ns
t
ON
ns
t
OFF
ns
ADDITIONAL APPLICATION CHARACTERISTICS
(GND = 0 V)
Symbol
BW
Parameter
Maximum On−Channel
Bandwidth or Minimum
Frequency Response
Off−Channel Feedthrough
Isolation
Condition
V
IS
=
½
(V
CC
−
V
EE
)
Source Amplitude = 0 dBm
(Figures 10 and 22)
f = 100 kHz; V
IS
=
½
(V
CC
−
V
EE
)
Source = 0 dBm
(Figures 12 and 22)
V
IS
=
½
(V
CC
−
V
EE
)
Source = 0 dBm
(Figures 10 and 22)
V
IN
= V
CC
to V
EE,
f
IS
= 1 kHz, t
r
= t
f
= 3 ns
R
IS
= 0
W,
C
L
= 1000 pF, Q = C
L
*
DV
OUT
(Figures 16 and 23)
f
IS
= 1 MHz, R
L
= 10 KW, C
L
= 50 pF,
V
IS
= 5.0 V
PP
sine wave
V
IS
= 6.0 V
PP
sine wave
(Figure 13)
V
CC
V
3.0
4.5
6.0
3.0
3.0
4.5
6.0
3.0
3.0
4.5
6.0
3.0
5.0
3.0
V
EE
V
0.0
0.0
0.0
−3.0
0.0
0.0
0.0
−3.0
0.0
0.0
0.0
−3.0
0.0
−3.0
Typ
25°C
145
165
180
180
−93
−93
−93
−93
−2
−2
−2
−2
9.0
12
Unit
MHz
V
ISO
dB
V
ONL
Maximum Feedthrough
On Loss
dB
Q
Charge Injection
pC
THD
Total Harmonic Distortion
THD + Noise
%
6.0
3.0
0.0
−3.0
0.10
0.05
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