data under multiple layers of advanced security to provide
the most secure key storage possible. To protect against
device-level security attacks, invasive and noninvasive
countermeasures are implemented including active die
shield, encrypted storage of keys, and algorithmic methods.
Benefits and Features
●
ECC-256 Compute Engine
•
FIPS 186 ECDSA P256 Signature and Verification
• ECDH Key Exchange with Authentication Prevents
Man-in-the-Middle Attacks
•
ECDSA Authenticated R/W of Configurable
Memory
●
FIPS 180 SHA-256 Compute Engine
• HMAC
●
SHA-256 OTP (One-Time Pad) Encrypted R/W of
Configurable Memory Through ECDH Established Key
●
Two GPIO Pins with Optional Authentication Control
• Open-Drain, 4mA/0.4V
• Optional SHA-256 or ECDSA Authenticated On/Off
and State Read
•
Optional ECDSA Certificate to Set On/Off after
Multiblock Hash for Secure Boot
●
RNG with NIST SP 800-90B Compliant Entropy
Source with Function to Read Out
●
Optional Chip Generated Pr/Pu Key Pairs for ECC
Operations
●
17-Bit One-Time Settable, Nonvolatile Decrement-
Only Counter with Authenticated Read
●
8Kbits of EEPROM for User Data, Keys, and
Certificates
●
Unique and Unalterable Factory Programmed 64-Bit
Identification Number (ROM ID)
• Optional Input Data Component to Crypto and Key
Operations
●
I
2
C Communication, 100kHz and 400kHz
●
Operating Range: 3.3V ±10%, -40°C to +85°C
●
6-Pin TDFN Package
Ordering Information
appears at end of data sheet.
Typical Application Circuit
appears at end of data sheet.
Applications
●
IoT Node Crypto-Protection
●
Accessory and Peripheral Secure Authentication
●
Secure Storage of Cryptographic Keys for a Host
Controller
●
Secure Boot or Download of Firmware and/or System
Parameters
19-8589; Rev 0; 7/16
ABRIDGED DATA SHEET
DS2476
DeepCover Secure Coprocessor
Absolute Maximum Ratings
Voltage Range on Any Pin Relative to GND ..........-0.5V to 4.0V
Maximum Current into Any Pin...........................................20mA
Operating Temperature Range ........................... -40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range ............................ -55°C to +125°C
Lead temperature (soldering, 10s) .................................. +300°C
Soldering Temperature (reflow) ...................................... +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(T
A
= -40°C to +85°C.) (Note 1)
PARAMETER
Supply Voltage
Active Supply Current
Standby Supply Current
Computation Current
GPIO
Output Low
Input Low
Input High
Leakage current
ECC ENGINE
Generate ECDSA Signature Time
Generate ECC Key Pair
Coprocessor ECDSA Verify Signature
or Compute ECDH Time
SHA-256 ENGINE
Computation Time (HMAC or RNG)
EEPROM
W/E Endurance
Read Memory Time
Write Memory Time
Data Retention
I
2
C SCL AND SDA PINS (Note 8)
Low-Level Input Voltage
High-Level Input Voltage
Hysteresis of Schmitt Trigger Inputs
Low-Level Output Voltage at 4mA Sink
Current
V
IL
V
IH
V
HYS
V
OL
(Note 9)
NCY
t
RM
t
WM
t
DR
T
A
=
+
85°C (Notes 6, 7)
10
0.15 ×
V
CC
V
CC
+
0.3V
0.05 ×
V
CC
0.4
(Notes 4, 5)
100K
1
15
—
ms
ms
years
t
CMP
Refer to full data sheet
ms
t
GES
t
GKP
t
VES
Refer to full data sheet
ms
ms
ms
PIO V
OL
PIO V
IL
PIO V
IH
I
L
-0.3
V
CC
x
0.7V
-10
0.4
V
CC
x
0.3V
V
CC
+
0.3V
+10
V
V
V
µA
SYMBOL
V
CC
I
CC
I
CCS
I
CMP
Refer to full data sheet
(Note 2)
CONDITIONS
MIN
2.97
TYP
3.3
MAX
3.63
300
250
UNITS
V
µA
µA
mA
-0.3
0.7 ×
V
CC
V
V
V
V
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Maxim Integrated
│
2
ABRIDGED DATA SHEET
DS2476
Electrical Characteristics (continued)
(T
A
= -40°C to +85°C.) (Note 1)
PARAMETER
Output Fall Time from V
IH(MIN)
to
V
IL(MAX)
with a Bus Capacitance from
10pF to 400pF
Pulse Width of Spikes that are
Suppressed by the Input Filter
Input Current with an Input Voltage
Between 0.1VCCmax and 0.9VCCmax
Input Capacitance
SCL Clock Frequency
Hold Time (Repeated) START
Condition
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated START
Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a STOP and
START Condition
Capacitive Load for Each Bus Line
Warm-Up Time
SYMBOL
t
OF
t
SP
II
CI
f
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
BUF
C
B
t
OSCWUP
(Notes 10, 14)
(Note 15)
(Notes 9, 11, 12)
(Note 13)
100
0.6
1.3
400
250
(Note 9)
(Note 10)
After this period, the first clock
pulse is generated
0
0.6
1.3
0.6
0.6
0.9
(Note 9)
(Note 9)
-10
10
400
CONDITIONS
MIN
TYP
30
50
+10
MAX
UNITS
ns
ns
µA
pF
kHz
µs
µs
µs
µs
µs
ns
µs
µs
pF
µs
DeepCover Secure Coprocessor
Note 1:
Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values at +25°C
Note 2:
Operating current continuously reading memory at 400kHz with < 25ns rise and fall times on SDA and SCL.
Note 3:
Refer to full data sheet.
Note 4:
Write-cycle endurance is tested in compliance with JESD47H.
Note 5:
Not 100% production tested; guaranteed by reliability qualification.
Note 6:
Data retention is tested in compliance with JESD47H.
Note 7:
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 8:
All I
2
C timing values are referred to V
IH(MIN)
and V
IL(MAX)
levels, except for t
OF
, whichis measured from V
IH(MIN)
to 0.3 x V
CC
.
Note 9:
Guaranteed by design and/or characterization only. Not production tested.
Note 10:
System requirement.
Note 11:
The DS2476 provides a hold time of at least 100ns for the SDA signal (referred to the V
IH(MIN)
of the SCL signal) to bridge
the undefined region of the falling edge of SCL. The master can provide a hold time of 0ns when writing to the device.
Note 12:
The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal. If the
clock stretches the SCL, the data must be valid by the set-up time before it releases the clock (I
2
C-bus specification Rev.
03, 19 June 2007).
Note 13:
A fast-mode I
2
C-bus device can be used in a standard-mode I
2
C-bus system, but the requirement t
SU:DAT
≥ 250ns must
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tr max + t
SU:DAT
= 1000 +
250 = 1250ns (according to the standard-mode I
2
C-bus specification) before the SCL line is released. Also, the acknowl-
edge timing must meet this set-up time. (I
2
C-bus specification Rev. 03, 19 June 2007)
Note 14:
C
B
= total capacitance of one bus line in pF. The maximum bus capacitance allowable can vary from this value depending
on the actual operating voltage and frequency of the application (I
2
C-bus specification Rev. 03, 19 June 2007).
Note 15:
I
2
C communication should not take place for max t
OSCWUP
time following a power-on reset.
Maxim Integrated
│
3
www.maximintegrated.com
ABRIDGED DATA SHEET
DS2476
DeepCover Secure Coprocessor
Pin Configuration
TOP VIEW
SCL 1
SDA
GND
2
3
TDFN-EP
(3mm
x
3mm)
6 V
CC
DS2476
5 PIOA
4 PIOB
Pin Description
PIN
1
2
3
4
5
6
—
NAME
SCL
SDA
GND
PIOB
PIOA
V
CC
EP
I
2
C CLK
I
2
C Data
Ground
General-Purpose IO
General-Purpose IO
Supply Voltage
Exposed Pad. Solder evenly to the board’s ground plane for proper
operation. Refer to Application Note 3273:
Exposed Pads: A Brief
Introduction
for additional information.
FUNCTION
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Maxim Integrated
│
4
ABRIDGED DATA SHEET
DS2476
DeepCover Secure Coprocessor
I
2
C
General Characteristics
The I
2
C bus uses a data line (SDA) plus a clock signal
(SCL) for communication. Both SDA and SCL are bidi-
rectional lines, connected to a positive supply voltage
through a pullup resistor. When there is no communica-
tion, both lines are high. The output stages of devices
connected to the bus must have an open drain or open
collector to perform the wired-AND function. Data on the
I
2
C bus can be transferred at rates of up to 100kbps in
standard mode and up to 400kbps in fast mode. The
DS2476 works in both modes.
A device that sends data on the bus is defined as a
transmitter, and a device receiving data is defined as a
receiver. The device that controls the communication is
called a master. The devices that are controlled by the
master are slaves. To be individually accessed, each
device must have a slave address that does not conflict
with other devices on the bus.
Data transfers can be initiated only when the bus is not
busy. The master generates the serial clock (SCL), con-
trols the bus access, generates the START and STOP
conditions, and determines the number of data bytes
transferred between START and STOP (Figure
41).
Data
is transferred in bytes with the most significant bit being
transmitted first. After each byte follows an acknowledge
bit to allow synchronization between master and slave.
Slave Address
The slave address to which the DS2476 responds is
shown in
Figure 42.
The slave address is part of the slave
address/control byte. The last bit of the slave address/
control byte (R/W) defines the data direction. When set
to 0, subsequent data flows from master to slave (write
access); when set to 1, data flows from slave to master
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