DS1868S-100- datasheet, PDF - EEWORLD Datasheet

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DS1868S-100-: DescriptionDigital Potentiometer ICs Dual; Categorysemiconductor Other integrated circuit (IC); File Size275KB，14 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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Digital Potentiometer ICs Dual

DS1868S-100- Parametric

Parameter Name	Attribute value
Product Category	Digital Potentiometer ICs
Manufacturer	Maxim
RoHS	Detailsxyybaxrtytscfxbawx
Resistance	100 kOhms
Temperature Coefficient	750 PPM / C
Tolerance	20 %
Number of POTs	Dual
Wiper Memory	Volatile
Digital Interface	Serial (3-Wire)
Operating Supply Voltage	2.7 V to 5.5 V
Operating Supply Current	400 uA
Maximum Operating Temperature	+ 85 C
Mounting Style	SMD/SMT
Package / Case	SOIC-16
Packaging	Tube
Description/Function	Dual digital potentiometer chip
Height	2.65 mm
Length	10.5 mm
Minimum Operating Temperature	- 40 C
Factory Pack Quantity	45
Supply Voltage - Max	5.5 V
Supply Voltage - Min	2.7 V
Taper	Linear
Width	7.6 mm
Unit Weight	0.023492 oz

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DS1868

Dual Digital Potentiometer Chip

www.dalsemi.com

FEATURES

Ultra-lowpower consumption, quiet, pumpless

design

Two digitally controlled, 256-position

potentiometers

Serial port provides means for setting and

reading both potentiometers

Resistors can be connected in series to

provide increased total resistance

20-pin TSSOP, 16-pin SOIC, and 14-pin DIP

packages are available.

Resistive elements are temperature

compensated to

±0.3

LSB relative linearity

Standard resistance values:

- DS1868-10

∼

10 kΩ

- DS1868-50

∼

50 kΩ

- DS1868-100

∼

100 kΩ

+5V or ±3V operation

Operating Temperature Range:

- Industrial: -40°C to 85°C

PIN ASSIGNMENT

DNC

RST

CLK

DNC

GND

DNC

OUT

DNC

OUT

W0 RST

L0 CLK

OUT

DQ GND

OUT

20-Pin TSSOP (173-mil)

RST

CLK

GND

DS1868S 16-Pin SOIC (300-mil)

14-Pin DIP (300-mil)

PIN DESCRIPTION

L0, L1

H0, H1

W0, W1

OUT

- Low End of Resistor

- High End of Resistor

- Wiper Terminal of Resistor

- Stacked Configuration Output

RST

- Serial Port Reset Input

- Serial Port Data Input

CLK

- Serial Port Clock Input

OUT

- Cascade Port Output

- +5 Volt Supply

GND

- Ground Connections

- No Internal Connection

- Substrate Bias Voltage

DNC

- Do Not Connect

*All GND pins must be connected to ground.

DESCRIPTION

The DS1868 Dual Digital Potentiometer Chip consists of two digitally controlled solid-state

potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section

and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the

1 of 14

100899

DS1868

wiper on the resistor array is set by an 8-bit value that controls which tap point is connected to the wiper

output. Communication and control of the device is accomplished via a 3-wire serial port interface. This

interface allows the device wiper position to be read or written.

Both potentiometers can be connected in series (or stacked) for an increased total resistance with the same

resolution. For multiple-device, single-processor environments, the DS1868 can be cascaded or daisy

chained. This feature provides for control of multiple devices over a single 3-wire bus.

The DS1868 is offered in three standard resistance values which include 10, 50, and 100 kohm versions.

The part is available in 16-pin SOIC (300-mil), 14-pin DIP, and 20-pin (173-mil) TSSOP packages.

OPERATION

The DS1868 contains two 256-position potentiometers whose wiper positions are set by an 8-bit value.

These two 8-bit values are written to a 17-bit I/O shift register which is used to store the two wiper

positions and the stack select bit when the device is powered. A block diagram of the DS1868 is

presented in Figure 1.

Communication and control of the DS1868 is accomplished through a 3-wire serial port interface that

drives an internal control logic unit. The 3-wire serial interface consists of the three input signals:

RST

CLK, and DQ.

The

RST

control signal is used to enable the 3-wire serial port operation of the device. The

RST

signal is

an active high input and is required to begin any communication to the DS1868. The CLK signal input is

used to provide timing synchronization for data input and output. The DQ signal line is used to transmit

potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift register of the

DS1868.

Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the

RST

signal input is low. Communication with the DS1868 requires the transition of the

RST

input from a low

state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low to

high transition of the CLK signal inputs. Three-wire serial timing requirements are provided in the timing

diagrams of Figure 9(b),(c).

Data written to the DS1868 over the 3-wire serial interface is stored in the 17-bit I/O shift register (see

Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the

stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift

Configuration. Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value.

Bit 1 will contain the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper

setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position

with the MSB for the wiper position occupying bit 9 and the LSB bit 16.

2 of 14

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