Changes to Figure 30 and Figure 32 .............................................14
9/03—Revision 0: Initial Version
Rev. C | Page 2 of 16
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
V
DD
= 5 V ± 10% or 3 V ± 10%; V
A
= +V
DD
; –40°C < T
A
< +125°C, unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity
2
Resistor Integral Nonlinearity
2
Nominal Resistor Tolerance
3
Resistance Temperature Coefficient
R
WB
RESISTOR TERMINALS
Voltage Range
4
Capacitance
5
B
Capacitance
5
W
Common-Mode Leakage
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance
5
POWER SUPPLIES
Power Supply Range
Supply Current
Symbol
R-DNL
R-INL
∆R
AB
(∆R
AB
/R
AB
)/∆T
R
WB
Conditions
R
WB
R
WB
T
A
= 25°C
Wiper = no connect
Code = 0x00, V
DD
= 5 V
Code = 0x00, V
DD
= 2.7 V
Min
–1.5
–4
–30
Typ
1
±0.1
±0.75
45
75
150
GND
f = 1 MHz, measured to GND, code = 0x40
f = 1 MHz, measured to GND, code = 0x40
45
60
1
2.4
0.8
2.1
0.6
±1
5
2.7
V
DD
= 5.5 V; V
IH
= V
DD
or V
IL
= GND
V
DD
= 5 V; V
IH
= V
DD
or V
IL
= GND
V
DD
= 3.3 V; V
IH
= V
DD
or V
IL
= GND
3
2.5
0.9
AD5246
Max
+1.5
+4
+30
150
400
V
DD
Unit
LSB
LSB
%
ppm/°C
Ω
Ω
V
pF
pF
nA
V
V
V
V
µA
pF
V
µA
µA
µA
V
B, W
C
B
C
W
I
CM
V
IH
V
IL
V
IH
V
IL
I
IL
C
IL
V
DD RANGE
I
DD
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 3 V
V
IN
= 0 V or 5 V
5.5
7
5.2
2
Power Dissipation
6
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
5, 7
Bandwidth –3 dB
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage Density
1
2
P
DISS
PSSR
BW_5K
THD
W
t
S
e
N_WB
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
V
DD
= +5 V ± 10%, code = midscale
R
AB
= 5 kΩ, code = 0x40
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz
V
A
= 5 V, ±1 LSB error band
R
WB
= 2.5 kΩ, R
S
= 0 Ω
±0.01
1.2
0.05
1
6
40
±0.025
µW
%/%
MHz
%
µs
nV/√Hz
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
Code = 0x7F.
4
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.
5
Guaranteed by design; not subject to production test.
6
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
Code = 0x7F.
4
Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other.
5
Guaranteed by design; not subject to production test.
6
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
7
All dynamic characteristics use V
DD
= 5 V.
Rev. C | Page 4 of 16
Data Sheet
TIMING CHARACTERISTICS
V
DD
= 5 V ± 10% or 3 V ± 10%; V
A
= V
DD
; –40°C < T
A
< +125°C, unless otherwise noted.
Table 3.
Parameter
I
2
C INTERFACE TIMING CHARACTERISTICS
2, 3, 4
SCL Clock Frequency
t
BUF
Bus Free Time Between STOP and START
t
HD;STA
Hold Time (Repeated START)
t
LOW
Low Period of SCL Clock
t
HIGH
High Period of SCL Clock
t
SU;STA
Setup Time for Repeated START Condition
t
HD;DAT
Data Hold Time
t
SU;DAT
Data Setup Time
t
F
Fall Time of Both SDA and SCL Signals
t
R
Rise Time of Both SDA and SCL Signals
t
SU;STO
Setup Time for STOP Condition
1
2
AD5246
Symbol
f
SCL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
Conditions
Min
Typ
1
Max
400
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
1.3
After this period, the first clock pulse is
generated
0.6
1.3
0.6
0.6
100
300
300
0.6
50
0.9
Typical specifications represent average readings at 25°C and V
DD
= 5 V.
Guaranteed by design; not subject to production test.
3
See timing diagrams (Figure 26, Figure 27, and Figure 28) for locations of measured values.
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