5962F9671802VRC datasheet, PDF

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5962F9671802VRC: DescriptionACT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDIP20, METAL SEALED, CERAMIC, DIP-20; Categorylogic logic; File Size70KB，3 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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5962F9671802VRC Overview

ACT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDIP20, METAL SEALED, CERAMIC, DIP-20

5962F9671802VRC Parametric

Parameter Name	Attribute value
Parts packaging code	DIP
package instruction	DIP, DIP20,.3
Contacts	20
Reach Compliance Code	unknown
Other features	RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHONOLOGY
Control type	ENABLE LOW
series	ACT
JESD-30 code	R-CDIP-T20
JESD-609 code	e4
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.012 A
Number of digits	4
Number of functions	2
Number of ports	2
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP20,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Prop。Delay @ Nom-Sup	10 ns
propagation delay (tpd)	10 ns
Certification status	Not Qualified
Filter level	38535V;38534K;883S
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
total dose	300k Rad(Si) V
width	7.62 mm
Base Number Matches	1

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ACTS244MS

January 1996

Radiation Hardened Octal

Non-Inverting Three-State Buffer

Pinouts

20 PIN CERAMIC DUAL-IN-LINE

MIL-STD-1835 DESIGNATOR CDIP2-T20,

LEAD FINISH C

TOP VIEW

AE

1

2

3

4

5

6

7

8

9

20 VCC

19 BE

18 AO1

17 BI4

16 AO2

15 BI3

14 AO3

13 BI2

12 AO4

11 BI1

tle

TS

MS

-

ia-

d-

l

-

rt-

e-

e

er)

hor

-

ds

r-

po-

n,

i-

or,

ia-

d-

,

Features

• Devices QML Qualified in Accordance with MIL-PRF-38535

• Detailed Electrical and Screening Requirements are Contained in

SMD# 5962-96718 and Intersil’s QM Plan

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

• Single Event Upset (SEU) Immunity: <1 x

(Typ)

10

-10

Errors/Bit/Day

AI1

BO4

AI2

BO3

AI3

BO2

AI4

BO1

• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm

2

/mg

• Dose Rate Upset . . . . . . . . . . . . . . . . >10

11

RAD (Si)/s, 20ns Pulse

• Dose Rate Survivability . . . . . . . . . . . >10

12

RAD (Si)/s, 20ns Pulse

• Latch-Up Free Under Any Conditions

• Military Temperature Range . . . . . . . . . . . . . . . . . . -55

o

C to +125

o

C

• Significant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

• Input Logic Levels

- VIL = 0.8V Max

- VIH = VCC/2 Min

• Input Current

≤

1µA at VOL, VOH

• Fast Propagation Delay . . . . . . . . . . . . . . . 14.5ns (Max), 10ns (Typ)

GND 10

20 PIN CERAMIC FLATPACK

MIL-STD-1835 DESIGNATOR CDFP4-F20,

LEAD FINISH C

TOP VIEW

AE

AI1

BO4

AI2

BO3

AI3

BO2

AI4

BO1

GND

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

VCC

BE

AO1

BI4

AO2

BI3

AO3

BI2

AO4

BI1

Description

The Intersil ACTS244MS is a Radiation Hardened Octal Non-Inverting

Three-State Buffer having two active low enable inputs.

The ACTS244MS utilizes advanced CMOS/SOS technology to achieve

high-speed operation. This device is a member of radiation hardened,

high-speed, CMOS/SOS Logic Family.

The ACTS244MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or

a Dual-In-Line Ceramic Package (D suffix).

Ordering Information

PART NUMBER

TEMPERATURE RANGE

-55

o

C to +125

o

C

-55

o

C to +125

o

C

25

o

C

25

o

C

25

o

C

SCREENING LEVEL

MIL-PRF-38535 Class V

Sample

Die

PACKAGE

20 Lead SBDIP

20 Lead Ceramic Flatpack

20 Lead SBDIP

20 Lead Ceramic Flatpack

Die

d,

L,

5962F9671801VRC

5962F9671801VXC

ACTS244D/Sample

ACTS244K/Sample

ACTS244HMSR

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Spec Number

File Number

1

518784

3187.1

5962F9671802VRC Related Products

	5962F9671802VRC	5962F9671802VXC	ACTS244KMSR-02	ACTS244DMSR-02
Description	ACT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDIP20, METAL SEALED, CERAMIC, DIP-20	ACT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDFP20, METAL SEALED, CERAMIC, DFP-20	ACT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDFP20, METAL SEALED, CERAMIC, DFP-20	ACT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDIP20, METAL SEALED, CERAMIC, DIP-20
Parts packaging code	DIP	DFP	DFP	DIP
package instruction	DIP, DIP20,.3	DFP, FL20,.3	METAL SEALED, CERAMIC, DFP-20	METAL SEALED, CERAMIC, DIP-20
Contacts	20	20	20	20
Reach Compliance Code	unknown	unknown	compliant	compliant
Other features	RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHONOLOGY	RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHONOLOGY	RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHONOLOGY	RADIATION HARD CMOS/SILICON ON SAPPHIRE (SOS) TECHONOLOGY
series	ACT	ACT	ACT	ACT
JESD-30 code	R-CDIP-T20	R-CDFP-F20	R-CDFP-F20	R-CDIP-T20
Logic integrated circuit type	BUS DRIVER	BUS DRIVER	BUS DRIVER	BUS DRIVER
Number of digits	4	4	4	4
Number of functions	2	2	2	2
Number of ports	2	2	2	2
Number of terminals	20	20	20	20
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C	-55 °C
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Output polarity	TRUE	TRUE	TRUE	TRUE
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP	DFP	DFP	DIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	FLATPACK	FLATPACK	IN-LINE
propagation delay (tpd)	10 ns	10 ns	10 ns	10 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	2.92 mm	2.92 mm	5.08 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V
surface mount	NO	YES	YES	NO
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY	MILITARY
Terminal form	THROUGH-HOLE	FLAT	FLAT	THROUGH-HOLE
Terminal pitch	2.54 mm	1.27 mm	1.27 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
width	7.62 mm	6.92 mm	6.92 mm	7.62 mm
JESD-609 code	e4	e4	-	e3
Load capacitance (CL)	50 pF	50 pF	50 pF	-
Terminal surface	GOLD	GOLD	-	Matte Tin (Sn)

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