Specifications
GAL22V10
GAL22V10
High Performance E
2
CMOS PLD
Generic Array Logic™
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.5 ns Maximum from Clock Input to Data Output
— UltraMOS
®
Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
I
Functional Block Diagram
I/CLK
RESET
8
OLMC
I/O/Q
I
10
OLMC
I/O/Q
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and UVCMOS 22V10 Devices
• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
— 90mA Typical Icc on Low Power Device
— 45mA Typical Icc on Quarter Power Device
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
ESCRIPTION
12
I
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(132X44)
14
OLMC
I
I/O/Q
16
OLMC
I
I/O/Q
I
16
OLMC
I/O/Q
I
14
OLMC
I/O/Q
I
12
OLMC
I/O/Q
I
10
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
PRESET
Description
The GAL22V10, at 4ns maximum propagation delay time, combines
a high performance CMOS process with Electrically Erasable (E
2
)
floating gate technology to provide the highest performance avail-
able of any 22V10 device on the market. CMOS circuitry allows
the GAL22V10 to consume much less power when compared to
bipolar 22V10 devices. E
2
technology offers high speed (<100ms)
erase times, providing the ability to reprogram or reconfigure the
device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V10 is fully function/fuse map/parametric com-
patible with standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
DIP
PLCC
I/CLK
I/O/Q
I/O/Q
Vcc
I
I
NC
I/CLK
I
I
25
I/O/Q
I/O/Q
1
24
Vcc
I/O/Q
I/O/Q
4
I
I
I
NC
I
I
I
11
12
I
I
2
28
26
5
I
I
I
6
7
23
I/O/Q
NC
GAL
22V10
18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GAL22V10
9
Top View
14
GND
NC
21
I/O/Q
I/O/Q
I
I
I
I
I
GND
12
16
I
I/O/Q
19
18
I/O/Q
I/O/Q
13
I
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
22v10_06
1
Specifications
GAL22V10
GAL22V10 Ordering Information
Commercial Grade Specifications
Tpd (ns)
4
5
Tsu (ns)
2.5
3
Tco (ns)
3.5
4
Icc (mA)
140
140
150
GAL22V10D-4LJ
GAL22V10D-5LJ
GAL22V10C-5LJ
GAL22V10D-7LP
GAL22V10C-7LP
Ordering #
Package
28-Lead PLCC
28-Lead PLCC
28-Lead PLCC
24-Pin Plastic DIP
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic Dip
28-Pin PLCC
7.5
4.5
5
4.5
6.5
4.5
4.5
4.5
5
140
140
140
140
140
GAL22V10D-7LJ or GAL22V10C-7LJ
GAL22V10B-7LP
GAL22V10B-7LJ
GAL22V10D-10QP
GAL22V10D-10QJ
GAL22V10D-10LP, GAL22V10C-10LP or GAL22V10B-10LP
GAL22V10D-10LJ, GAL22V10C-10LJ or GAL22V10B-10LJ
GAL22V10D-15QP or GAL22V10B-15QP
GAL22V10D-15QJ or GAL22V10B-15QJ
GAL22V10D-15LP or GAL22V10B-15LP
GAL22V10D-15LJ or GAL22V10B-15LJ
GAL22V10D-25QP or GAL22V10B-25QP
GAL22V10D-25QJ or GAL22V10B-25QJ
GAL22V10D-25LP or GAL22V10B-25LP
GAL22V10D-25LJ or GAL22V10B-25LJ
10
7
7
55
55
130
130
15
10
8
55
55
130
130
25
15
15
55
55
90
90
Industrial Grade Specifications
Tpd (ns)
7.5
Tsu (ns)
5
4.5
Tco (ns)
4.5
4.5
7
Icc (mA)
160
160
160
160
Ordering #
GAL22V10D-7LPI or GAL22V10C-7LPI
GAL22V10D-7LJI or GAL22V10C-7LJI
GAL22V10D-10LPI or GAL22V10C-10LPI
GAL22V10D-10LJI or GAL22V10C-10LJI
GAL22V10D-15LPI or GAL22V10B-15LPI
GAL22V10D-15LJI or GAL22V10B-15LJI
GAL22V10D-20LPI or GAL22V10B-20LPI
GAL22V10D-20LJI or GAL22V10B-20LJI
GAL22V10D-25LPI or GAL22V10B-25LPI
GAL22V10D-25LJI or GAL22V10B-25LJI
Package
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
24-Pin Plastic DIP
28-Lead PLCC
10
7
15
10
8
150
150
20
14
10
150
150
25
15
15
150
150
Part Number Description
XXXXXXXX
_
XX
X X X
GAL22V10D
Device Name
GAL22V10C
GAL22V10B
Speed (ns)
L = Low Power
Power
Q = Quarter Power
Grade
Blank = Commercial
I = Industrial
Package
P = Plastic DIP
J = PLCC
2
Specifications
GAL22V10
Output Logic Macrocell (OLMC)
The GAL22V10 has a variable number of product terms per OLMC.
Of the ten available OLMCs, two OLMCs have access to eight
product terms (pins 14 and 23, DIP pinout), two have ten product
terms (pins 15 and 22), two have twelve product terms (pins 16 and
21), two have fourteen product terms (pins 17 and 20), and two
OLMCs have sixteen product terms (pins 18 and 19). In addition
to the product terms available for logic, each OLMC has an addi-
tional product-term dedicated to output enable control.
The output polarity of each OLMC can be individually programmed
to be true or inverting, in either combinatorial or registered mode.
This allows each output to be individually configured as either active
high or active low.
The GAL22V10 has a product term for Asynchronous Reset (AR)
and a product term for Synchronous Preset (SP). These two prod-
uct terms are common to all registered OLMCs. The Asynchronous
Reset sets all registers to zero any time this dedicated product term
is asserted. The Synchronous Preset sets all registers to a logic
one on the rising edge of the next clock pulse after this product term
is asserted.
NOTE: The AR and SP product terms will force the Q output of the
flip-flop into the same state regardless of the polarity of the output.
Therefore, a reset operation, which sets the register output to a zero,
may result in either a high or low at the output pin, depending on
the pin polarity chosen.
A R
D
Q
CLK
SP
Q
4 TO 1
MUX
2 TO 1
MUX
GAL22V10 OUTPUT LOGIC MACROCELL (OLMC)
Output Logic Macrocell Configurations
Each of the Macrocells of the GAL22V10 has two primary functional
modes: registered, and combinatorial I/O. The modes and the
output polarity are set by two bits (SO and S1), which are normally
controlled by the logic compiler. Each of these two primary modes,
and the bit settings required to enable them, are described below
and on the following page.
REGISTERED
In registered mode the output pin associated with an individual
OLMC is driven by the Q output of that OLMC’s D-type flip-flop.
Logic polarity of the output signal at the pin may be selected by
specifying that the output buffer drive either true (active high) or
inverted (active low). Output tri-state control is available as an in-
dividual product-term for each OLMC, and can therefore be defined
by a logic equation. The D flip-flop’s /Q output is fed back into the
AND array, with both the true and complement of the feedback
available as inputs to the AND array.
NOTE: In registered mode, the feedback is from the /Q output of
the register, and not from the pin; therefore, a pin defined as reg-
istered is an output only, and cannot be used for dynamic
I/O, as can the combinatorial pins.
COMBINATORIAL I/O
In combinatorial mode the pin associated with an individual OLMC
is driven by the output of the sum term gate. Logic polarity of the
output signal at the pin may be selected by specifying that the output
buffer drive either true (active high) or inverted (active low). Out-
put tri-state control is available as an individual product-term for
each output, and may be individually set by the compiler as either
“on” (dedicated output), “off” (dedicated input), or “product-term
driven” (dynamic I/O). Feedback into the AND array is from the pin
side of the output enable buffer. Both polarities (true and inverted)
of the pin are fed back into the AND array.
3
Specifications
GAL22V10
Registered Mode
AR
AR
D
Q
D
Q
CLK
SP
Q
CLK
SP
Q
ACTIVE LOW
S
0
= 0
S
1
= 0
S
0
= 1
S
1
= 0
ACTIVE HIGH
Combinatorial Mode
ACTIVE LOW
S
0
= 0
S
1
= 1
S
0
= 1
S
1
= 1
ACTIVE HIGH
4
Specifications
GAL22V10
GAL22V10 Logic Diagram / JEDEC Fuse Map
DIP (PLCC) Package Pinouts
1 (2)
0
0000
0044
.
.
.
0396
4
8
12
16
20
24
28
32
36
40
ASYNCHRONOUS RESET
(TO ALL REGISTERS)
8
OLMC
S0
5808
S1
5809
23 (27)
0440
.
.
.
.
0880
10
OLMC
S0
5810
S1
5811
22 (26)
2 (3)
0924
.
.
.
.
.
1452
12
OLMC
S0
5812
S1
5813
21 (25)
3 (4)
1496
.
.
.
.
.
.
2112
14
OLMC
S0
5814
S1
5815
20 (24)
4 (5)
2156
.
.
.
.
.
.
.
2860
16
OLMC
S0
5816
S1
5817
19 (23)
5 (6)
2904
.
.
.
.
.
.
.
3608
16
OLMC
S0
5818
S1
5819
18 (21)
6 (7)
3652
.
.
.
.
.
.
4268
14
OLMC
S0
5820
S1
5821
17 (20)
7 (9)
4312
.
.
.
.
.
4840
12
OLMC
S0
5822
S1
5823
16 (19)
8 (10)
4884
.
.
.
.
5324
10
OLMC
S0
5824
S1
5825
15 (18)
9 (11)
5368
.
.
.
5720
8
OLMC
S0
5826
S1
5827
14 (17)
10 (12)
5764
11 (13)
5828, 5829 ...
M
S
B
L
S
B
SYNCHRONOUS PRESET
(TO ALL REGISTERS)
13 (16)
Electronic Signature
... 5890, 5891
Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0
5