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GAL22V10C-10LJI

Description
EE PLD, 10 ns, PDIP24
CategoryProgrammable logic devices    Programmable logic   
File Size386KB,29 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Download Datasheet Parametric View All

GAL22V10C-10LJI Overview

EE PLD, 10 ns, PDIP24

GAL22V10C-10LJI Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerLattice
Parts packaging codeQLCC
package instructionQCCJ, LDCC28,.5SQ
Contacts28
Reach Compliance Codecompli
ECCN codeEAR99
Other featuresREGISTER PRELOAD; POWER-UP RESET
ArchitecturePAL-TYPE
maximum clock frequency71.4 MHz
JESD-30 codeS-PQCC-J28
JESD-609 codee0
length11.5062 mm
Humidity sensitivity level1
Dedicated input times11
Number of I/O lines10
Number of entries22
Output times10
Number of product terms132
Number of terminals28
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize11 DEDICATED INPUTS, 10 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC28,.5SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Programmable logic typeEE PLD
propagation delay10 ns
Certification statusNot Qualified
Maximum seat height4.572 mm
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width11.5062 mm
Specifications
GAL22V10
GAL22V10
High Performance E
2
CMOS PLD
Generic Array Logic™
Features
• HIGH PERFORMANCE E
2
CMOS
®
TECHNOLOGY
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.5 ns Maximum from Clock Input to Data Output
— UltraMOS
®
Advanced CMOS Technology
• ACTIVE PULL-UPS ON ALL PINS
I
Functional Block Diagram
I/CLK
RESET
8
OLMC
I/O/Q
I
10
OLMC
I/O/Q
• COMPATIBLE WITH STANDARD 22V10 DEVICES
— Fully Function/Fuse-Map/Parametric Compatible
with Bipolar and UVCMOS 22V10 Devices
• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
— 90mA Typical Icc on Low Power Device
— 45mA Typical Icc on Quarter Power Device
• E
2
CELL TECHNOLOGY
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• TEN OUTPUT LOGIC MACROCELLS
— Maximum Flexibility for Complex Logic Designs
• PRELOAD AND POWER-ON RESET OF REGISTERS
— 100% Functional Testability
• APPLICATIONS INCLUDE:
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
ESCRIPTION
12
I
OLMC
I/O/Q
PROGRAMMABLE
AND-ARRAY
(132X44)
14
OLMC
I
I/O/Q
16
OLMC
I
I/O/Q
I
16
OLMC
I/O/Q
I
14
OLMC
I/O/Q
I
12
OLMC
I/O/Q
I
10
OLMC
I/O/Q
I
8
OLMC
I/O/Q
I
PRESET
Description
The GAL22V10, at 4ns maximum propagation delay time, combines
a high performance CMOS process with Electrically Erasable (E
2
)
floating gate technology to provide the highest performance avail-
able of any 22V10 device on the market. CMOS circuitry allows
the GAL22V10 to consume much less power when compared to
bipolar 22V10 devices. E
2
technology offers high speed (<100ms)
erase times, providing the ability to reprogram or reconfigure the
device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V10 is fully function/fuse map/parametric com-
patible with standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Pin Configuration
DIP
PLCC
I/CLK
I/O/Q
I/O/Q
Vcc
I
I
NC
I/CLK
I
I
25
I/O/Q
I/O/Q
1
24
Vcc
I/O/Q
I/O/Q
4
I
I
I
NC
I
I
I
11
12
I
I
2
28
26
5
I
I
I
6
7
23
I/O/Q
NC
GAL
22V10
18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GAL22V10
9
Top View
14
GND
NC
21
I/O/Q
I/O/Q
I
I
I
I
I
GND
12
16
I
I/O/Q
19
18
I/O/Q
I/O/Q
13
I
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2000
22v10_06
1

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