Multirate to 2.7 Gb/s Clock and Data
Recovery IC with Integrated Limiting Amp
ADN2819
FEATURES
Meets SONET requirements for jitter
transfer/generation/tolerance
Quantizer sensitivity: 4 mV typical
Adjustable slice level: ±100 mV
1.9 GHz minimum bandwidth
Patented clock recovery architecture
Loss of signal detect range: 3 mV to 15 mV
Single reference clock frequency for all rates, including
15/14 (7%) wrapper rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz
REFCLK
LVPECL/LVDS/LVCMOS/LVTTL compatible inputs
(LVPECL/LVDS only at 155.52 MHz)
19.44 MHz oscillator on-chip to be used with external crystal
Loss of lock indicator
Loopback mode for high speed test data
Output squelch and bypass features
Single-supply operation: 3.3 V
Low power: 540 mW typical
7 mm × 7 mm 48-lead LFCSP
PRODUCT DESCRIPTION
The ADN2819 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at rates of OC-3,
OC-12, OC-48, Gigabit Ethernet, and 15/14 FEC rates. All
SONET jitter requirements are met, including jitter transfer,
jitter generation, and jitter tolerance. All specifications are
quoted for –40°C to +85°C ambient temperature, unless
otherwise noted.
The device is intended for WDM system applications, and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both native rates and 15/14 rate
digital wrappers are supported by the ADN2819, without any
change of reference clock.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.
The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user-adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at the
output.
The ADN2819 is available in a compact 7 mm × 7 mm, 48-lead
chip scale package.
APPLICATIONS
SONET OC-3/-12/-48, SDH STM-1/-4/-16, GbE and 15/14
FEC rates
WDM transponders
Regenerators/repeaters
Test equipment
Backplane applications
FUNCTIONAL BLOCK DIAGRAM
SLICEP/N
VCC
VEE
CF1
CF2
LOL
2
PIN
QUANTIZER
NIN
ADN2819
LOOP
FILTER
/n
XTAL
OSC
2
2
REFSEL[0..1]
REFCLKP/N
XO1
PHASE
SHIFTER
PHASE
DET.
LOOP
FILTER
VCO
FREQUENCY
LOCK
DETECTOR
XO2
VREF
LEVEL
DETECT
DATA
RETIMING
2
THRADJ
SDOUT
DATAOUTP/N
2
CLKOUTP/N
SEL[0..2]
DIVIDER
1/2/4/16
FRACTIONAL
DIVIDER
3
REFSEL
02999-0-001
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADN2819
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Definition of Terms.......................................................................... 9
Maximum, Minimum, and Typical Specifications ................... 9
Input Sensitivity and Input Overdrive....................................... 9
Single-Ended vs. Differential ...................................................... 9
LOS Response Time ................................................................... 10
Jitter Specifications..................................................................... 10
Theory of Operation ...................................................................... 12
Functional Description .................................................................. 14
Multirate Clock and Data Recovery......................................... 14
Limiting Amplifier ..................................................................... 14
Slice Adjust .................................................................................. 14
Loss of Signal (LOS) Detector .................................................. 14
Reference Clock.......................................................................... 14
Lock Detector Operation .......................................................... 15
Squelch Mode ............................................................................. 16
Test Modes: Bypass and Loopback........................................... 16
Applications Information .............................................................. 17
PCB Design Guidelines ............................................................. 17
Choosing AC-Coupling Capacitors ......................................... 19
DC-Coupled Application .......................................................... 20
LOL Toggling During Loss of Input Data............................... 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
5/04—Data Sheet Changed from Rev. A to Rev. B
Updated Format..............................................................Universal
Changes to Specifications ............................................................ 3
Changes to Table 7 and Table 8................................................. 15
Updated Outline Dimensions ................................................... 21
Changes to Ordering Guide ...................................................... 21
1/03—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Table IV ................................................................... 12
Updated OUTLINE DIMENSIONS ........................................ 16
Rev. B | Page 2 of 24
ADN2819
SPECIFICATIONS
Table 1. T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
= 4.7 µF, SLICEP = SLICEN = VCC, unless otherwise noted.
Parameter
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Input Common-Mode Level
Differential Input Sensitivity
Input Overdrive
Input Offset
Input rms Noise
QUANTIZER—AC CHARACTERISTICS
Upper –3 dB Bandwidth
Small Signal Gain
S11
Input Resistance
Input Capacitance
Pulse Width Distortion
2
QUANTIZER SLICE ADJUSTMENT
Gain
Control Voltage Range
Slice Threshold Offset
LEVEL SIGNAL DETECT (SDOUT)
Level Detect Range (See Figure 4)
Conditions
@ PIN or NIN, dc-coupled
DC-coupled (See Figure 28)
PIN-NIN, ac-coupled
1
, BER = 1 × 10
–10
See Figure 8
BER = 1 × 10
–10
Min
0
0.4
4
2
500
244
1.9
54
–15
100
0.65
10
0.11
–0.8
1.3
0.20
0.30
+0.8
VCC
10
5
Typ
Max
1.2
2.4
Unit
V
V
V
mV p-p
mV p-p
µV
µV rms
GHz
dB
dB
Ω
pF
ps
V/V
V
V
mV
mV
mV
mV
µs
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Differential
@ 2.5 GHz
Differential
SLICEP–SLICEN = ±0.5 V
SLICEP–SLICEN
@ SLICEP or SLICEN
±1.0
R
THRESH
= 2 Ω
R
THRESH
= 20 kΩ
R
THRESH
= 90 kΩ
DC-coupled
OC-48, PRBS 2
23
R
THRESH
= 2 kΩ
R
THRESH
= 20 kΩ
R
THRESH
= 90 kΩ
OC-12, PRBS 2
23
R
THRESH
= 2 kΩ
R
THRESH
= 20 kΩ
R
THRESH
= 90 kΩ
R
THRESH
= 90 kΩ @ 25°C
OC-3, PRBS 2
23
R
THRESH
= 2 kΩ
R
THRESH
= 20 kΩ
R
THRESH
= 90 kΩ
R
THRESH
= 90 kΩ @ 25°C
OC-48, PRBS 2
7
R
THRESH
= 2 kΩ
R
THRESH
= 20 kΩ
R
THRESH
= 90 kΩ
OC-12, PRBS 2
7
R
THRESH
= 2 kΩ
R
THRESH
= 20 kΩ
R
THRESH
= 90 kΩ
9.4
2.5
0.7
0.1
5.6
3.9
3.2
4.7
1.8
4.8
3.6
13.3
5.3
3.0
0.3
6.6
6.2
6.7
6.4
6.0
6.3
6.9
6.2
5.6
5.6
6.6
6.6
6.2
6.7
6.6
6.2
6.7
18.0
7.6
5.2
5
7.8
8.5
9.9
7.8
10.0
8.9
8.5
Response Time
Hysteresis (Electrical)
3.4
5.6
3.9
3.2
5.7
3.9
3.2
9.9
7.8
8.5
9.9
7.8
8.5
9.9
Rev. B | Page 3 of 24
ADN2819
Parameter
Hysteresis (Electrical) (continued)
Conditions
OC-3, PRBS 2
7
R
THRESH
= 2 kΩ
R
THRESH
= 20 kΩ
R
THRESH
= 90 kΩ
From f
VCO
error > 1000 ppm
3.0
150
PIN–NIN = 10 mV p-p
OC-48
GbE
OC-12
OC-3
OC-48
OC-12
OC-3
OC-48, 12 kHz–20 MHz
OC-12, 12 kHz–5 MHz
0.02
OC-3, 12 kHz–1.3 MHz
0.02
Jitter Tolerance
OC-48 (See Figure 14)
600 Hz
3
6 kHz
3
100 kHz
1 MHz
3
GbE (OC-24) (See Figure 14)
300 Hz
3
3 kHz
3
50 kHz
500 kHz
3
OC-12 (See Figure 14)
30 Hz
3
300 Hz
25 kHz
250 kHz
3
OC-3 (See Figure 14)
30 Hz
3
300 Hz
3
6500 Hz
65 kHz
3
V
SE
(See Figure 7)
V
DIFF
(See Figure 7)
V
OH
V
OL
, referred to VCC
20%–80%
80%–20%
92
20
5.5
1.0
16
16
7.7
2.2
100
44
5.8
1.0
50
23.5
6.0
1.0
300
600
–0.60
455
910
VCC
600
1200
–0.30
150
150
Min
5.4
4.6
3.9
Typ
6.6
6.4
6.8
60
3.3
164
590
310
140
48
0.025
0.004
0.002
0.05
Max
7.7
8.2
9.7
Unit
dB
dB
dB
mV
V
mA
kHz
kHz
kHz
kHz
dB
dB
dB
UI rms
UI p-p
UI rms
UI p-p
UI rms
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
mV
mV
V
V
ps
ps
LOSS OF LOCK DETECTOR (LOL)
Loss of Lock Response Time
POWER SUPPLY VOLTAGE
POWER SUPPLY CURRENT
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer BW
3.6
215
880
480
200
85
Jitter Peaking
Jitter Generation
0.003
0.09
0.002
0.04
0.002
0.04
CML OUTPUTS (CLKOUTP/N, DATAOUTP/N)
Single-Ended Output Swing
Differential Output Swing
Output High Voltage
Output Low Voltage
Rise Time
Fall Time
Rev. B | Page 4 of 24
ADN2819
Parameter
Setup Time
Conditions
T
S
(See Figure 3)
OC-48
GbE
OC-12
OC-3
T
H
(See Figure 3)
OC-48
GbE
OC-12
OC-3
@ REFCLKP or REFCLKN
DC-coupled, single-ended
CML inputs
Min
140
350
750
3145
150
350
750
3150
0
100
VCC/2
0.8
V
IH
V
IL
V
IN
= 0.4 V or V
IN
= 2.4 V
V
IN
= 0.4 V or V
IN
= 2.4 V
V
OH
, I
OH
= –2.0 mA
V
OL
, I
OL
= +2.0 mA
2.0
–5
–5
2.4
0.4
V
0.8
+5
+50
V
µA
µA
V
V
VCC
Typ
Max
Unit
ps
ps
ps
ps
ps
ps
ps
ps
V
mV
V
V
Hold Time
REFCLK DC INPUT CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Common-Mode Level
TEST DATA DC INPUT CHARACTERISTICS
4
(TDINP/N)
Peak-to-Peak Differential Input Voltage
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
Input Current (SEL0 and SEL1 Only)
5
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
1
2
PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity.
PWD measurement made on quantizer outputs in bypass mode.
3
Jitter tolerance measurements are equipment limited.
4
TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.
5
SEL0 and SEL1 have internal pull-down resistors, causing higher I
IH
.
Rev. B | Page 5 of 24
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