16-Bit, 65 MSPS,
1.8 V Analog-to-Digital Converter
Enhanced Product
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
77.6 dBFS at 9.7 MHz input
76.4 dBFS at 70 MHz input
SFDR
94 dBc at 9.7 MHz input
93 dBc at 70 MHz input
Low power
111 mW at 65 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = −0.5/+1.0 LSB
Interleaved data output for reduced pin-count interface
Serial port control options
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1 to 8 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
RBIAS
VCM
VIN+
VIN–
AVDD
AGND
AD9266-EP
FUNCTIONAL BLOCK DIAGRAM
SDIO SCLK CSB
DRVDD
SPI
CMOS
OUTPUT BUFFER
AD9266-EP
OR
D15_D14
8
D1_D0
DCO
PROGRAMMING DATA
ADC
CORE
VREF
SENSE
REF
SELECT
DIVIDE
1 TO 8
DUTY CYCLE
STABILIZER
MODE
CONTROLS
CLK+ CLK–
PDWN DFS MODE
Figure 1.
PRODUCT HIGHLIGHTS
1.
The
AD9266-EP
operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
The sample-and-hold circuit maintains excellent performance
at high input frequencies and is designed for low cost, low
power, and ease of use.
A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO and data output
(D15_D14 to D1_D0) timing and offset adjustments, and
voltage reference modes.
The
AD9266-EP
is packaged in a 32-lead RoHS-compliant
LFCSP that is pin compatible with the
AD9609
10-bit
ADC, the
AD9629
12-bit ADC, and the
AD9649
14-bit
ADC, enabling a simple migration path between 10-bit and
16-bit converters sampling at 65 MSPS.
2.
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC standard)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
Enhanced product change notification
Qualification data available on request
3.
4.
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
PET/SPECT imaging
Rev. B
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10476-001
AD9266-EP
TABLE OF CONTENTS
Features .............................................................................................. 1
Enhanced Product Features ............................................................ 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Enhanced Product
Digital Specifications ....................................................................6
Switching Specifications ...............................................................7
Timing Specifications ...................................................................8
Absolute Maximum Ratings ............................................................9
Thermal Characteristics ...............................................................9
ESD Caution...................................................................................9
Pin Configuration and Function Descriptions........................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
3/16—Rev. A to Rev. B
Change to Product Highlights ........................................................ 1
Changes to General Description .................................................... 3
Change to Pipeline Delay (Latency) Parameter, Table 4 ............. 7
Changes to Figure 3 and Table 8 ................................................... 10
7/12—Rev. 0 to Rev. A
Changes to Resolution Parameter, Table 1 and Note 3, Table 1 ........ 4
1/12—Revision 0: Initial Version
Rev. B | Page 2 of 12
Enhanced Product
GENERAL DESCRIPTION
The
AD9266-EP
is a monolithic, single-channel 1.8 V supply,
16-bit, 65 MSPS analog-to-digital converter (ADC). It features a
high performance sample-and-hold circuit and on-chip voltage
reference.
The product uses multistage differential pipeline architecture
with output error correction logic to provide 16-bit accuracy at
65 MSPS data rates and to guarantee no missing codes over the
full operating temperature range.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).
AD9266-EP
A differential clock input with a selectable internal 1-to-8 divide
ratio controls all internal conversion cycles. An optional duty cycle
stabilizer (DCS) compensates for wide variations in the clock duty
cycle while maintaining excellent overall ADC performance.
The interleaved digital output data is presented in offset binary,
gray code, or twos complement format. A data clock output (DCO)
is provided to ensure proper latch timing with receiving logic.
CMOS levels from 1.8 V through 3.3 V are supported.
The
AD9266-EP
is available in a 32-lead RoHS compliant LFCSP
and is specified over the −55°C to +125°C temperature range.
Additional application and technical information can be found
in the
AD9266
data sheet.
Rev. B | Page 3 of 12
AD9266-EP
SPECIFICATIONS
DC SPECIFICATIONS
Enhanced Product
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Integral Nonlinearity (INL)
2
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation Error at 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance
3
Input Common-Mode Voltage
Input Common-Mode Range
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD
2
IDRVDD
2
(1.8 V)
IDRVDD
2
(3.3 V)
POWER CONSUMPTION
DC Input
Sine Wave Input
2
(DRVDD = 1.8 V)
Sine Wave Input
2
(DRVDD = 3.3 V)
Standby Power
4
Power-Down Power
1
2
Temp
Full
Full
Full
25°C
Full
25°C
Full
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
Full
Min
16
Typ
Max
Unit
Bits
Guaranteed
+0.05
−1.3
−0.5/+1.0
±0.30
−0.9/+1.7
±6.5
±2.6
±2
0.983
0.995
2
2.8
2
6.5
0.9
0.5
7.5
1.3
1.007
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
V
mV
LSB rms
V p-p
pF
V
V
kΩ
Full
Full
Full
25°C
25°C
25°C
Full
25°C
25°C
25°C
1.7
1.7
1.8
1.9
3.6
62.2
V
V
mA
mA
mA
mW
mW
mW
mW
mW
56.3
5.2
9.3
107
111
132
44
0.5
122
Measured with 1.0 V external reference.
Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between the differential inputs.
4
Standby power is measured with a dc input and the CLK active.
Rev. B | Page 4 of 12
Enhanced Product
AC SPECIFICATIONS
AD9266-EP
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 2.
Parameter
1
SIGNAL-TO-NOISE RATIO (SNR)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
WORST SECOND OR THIRD HARMONIC
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
WORST OTHER (HARMONIC OR SPUR)
f
IN
= 9.7 MHz
f
IN
= 30.5 MHz
f
IN
= 70 MHz
TWO-TONE SFDR
f
IN
= 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS)
ANALOG INPUT BANDWIDTH
1
Temp
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
25°C
25°C
Min
Typ
77.6
77.4
Max
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MHz
76.5
76.4
77.4
77.2
76.0
76.3
12.6
12.5
12.3
12.4
−94
−93
−80
−93
94
93
80
93
−92
−101
−88
−98
90
700
See the
AN-835
Application Note,
Understanding High Speed ADC Testing and Evaluation,
for a complete set of definitions.
Rev. B | Page 5 of 12
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