NB4N527SMNEVB
Evaluation Board User's
Manual for NB4N527S
http://onsemi.com
EVAL BOARD USER’S MANUAL
INTRODUCTION
ON Semiconductor has developed an evaluation board for
the NB4N527S device as a convenience for the customers
interested in performing their own device engineering
assessment. This board provides a high bandwidth 50
W
controlled impedance environment. The pictures in Figure 1
show the top and bottom view of the evaluation board, which
can be configured in several different ways.
This evaluation board manual contains:
•
Information on 16−lead QFN Evaluation Board
•
Assembly Instructions
•
Appropriate Lab Setup
•
Bill of Materials
This manual should be used in conjunction with the
NB4N527S device data sheet, which contains full technical
details on the device specifications and operation.
Board Lay−Up
The 16−lead QFN evaluation board is implemented in
four layers with split (dual) power supplies (Figure 2,
Evaluation Board Lay−up). For standard lab setup, a split
(dual) power supply is essential to enable the 50
W
internal
impedance in the oscilloscope as a device termination. The
first layer or primary trace layer is 0.005, thick Rogers
RO6002 material, which is designed to have equal electrical
length on all signal traces from the device under the test
(DUT) to the sense output. The second layer is the 1.0 oz.
copper ground plane. The FR4 dielectric material is placed
between the second and third layer, and between the third
and fourth layer. The third layer is also a 1.0 oz copper
ground plane. The fourth layer is the secondary trace layer.
Top View
Bottom View
Figure 1. Top and Bottom View of the 16 QFN Evaluation Board
©
Semiconductor Components Industries, LLC, 2012
February, 2012
−
Rev. 2
1
Publication Order Number:
EVBUM2077/D
NB4N527SMNEVB
Figure 2. Evaluation Board Lay−up
Connecting Power and Ground Planes
Top side of the evaluation board has the four surfaces
mount test point clips labeled V
CC
, V
EE
, SMA_GND, and
DUT_GND. DUT_GND is connected to the exposed flag of
the QFN package. For proper operation, the exposed flag is
recommended to be
ELECTRICALLY
left floating or tied
Table 1. Power Supply Levels
Power Supply Span
3.0 V
3.3 V
3.6 V
V
CC
1.75 V
2.05 V
2.35 V
to V
EE
, but must be
THERMALLY
connected to a
sufficient heat conduit such as a thermal plane Exact supply
voltage values that need to be applied can be found in
Table 1 and Figures 4 and 5.
V
EE
−1.25
V
−1.25
V
−1.25
V
SMA_GND
0V
0V
0V
DUT_GND
Float or V
EE
Float or V
EE
Float or V
EE
Stimulus (Generator) Termination
All ECL outputs need to be terminated to V
TT
(V
TT
= V
CC
–2.0 V = GND) via a 50
W
resistor. The current board design
utilizes the internal resistors and the V
TDx
pins are wired to
ground. (More information on termination is provided in
AN8020). If evaluation does not require use of internal
termination resistors, 0402 chip resistor pads are provided
on the bottom side of the evaluation board. The jumper wires
of the V
TDx
pin pads should be removed (J1, J4, J13 and J15
to SMA_GND jumper). Solder the chip resistors to the
bottom side of the board between the appropriate input of the
device pin pads and the ground pads (for split power supply
setup).
Likewise for CML outputs, CML stimulus signal need to
be terminated to V
CC
via a 50
W
resistor. If internal resistors
are used, the V
TDx
pin pads should be wired to V
CC
. To
accomplish this configuration, the jumper wire has to be
moved from SMA_GND ring to V
CC
ring on the bottom of
the board.
Table 2. SMA Connectors and Jumpers Placement
Device
Pin #
Connector
Wire
J1
1
No
SMA_GND
J2
2
Yes
No
J3
3
Yes
No
J4
4
No
SMA_GND
J5
5
No
V
EE
J6
6
No
No
J7
7
No
No
J8
8
No
For the LVDS configuration, V
TDx
pin pads of the D0 or
D1 input has to be shorted to form 100
W
across differential
lines. This configuration is accomplished by moving the
jumper wire from SMA_GND ring to complementary V
TDx
pin pad (example: VTD0 and VTD0b for D0 input and
VTD1 and VTD1b for D1 input).
DUT Termination
For standard lab setup and test, a split (dual) power supply
is required enabling the 50
W
internal impedance in the
oscilloscope to be used as a termination of the signals (in
split power supply setup SMA_GND is the system ground,
V
CC
is varied, and V
EE
is –1.25 V; see Table 1, Power
Supply Levels).
Board Components Configuration
The NB4N527SMNEVB evaluation board requires eight
side SMA connectors. Placement locations are described in
Table 2 and Figure 3.
J9
9
Yes
No
J10
10
Yes
No
J11
11
Yes
No
J12
12
No
No
J13
13
No
SMA_GND
J14
14
Yes
No
J15
15
Yes
No
J16
16
No
SMA_GND
V
CC
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