DS1WM
Synthesizable 1-Wire Bus Master
www.maxim-ic.com
FEATURES
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Memory maps into any standard byte-wide
data bus.
Eliminates CPU “bit-banging” by internally
generating all 1-Wire
®
timing and control
signals.
Generates interrupts to provide for more
efficient programming.
Search ROM Accelerator relieves CPU from
any single bit operations on the 1-Wire Bus.
Supports Overdrive mode and slave
interrupts.
Capable of running off any system clock from
3.2MHz to 128MHz.
Small size: all digital design, only 1500 gates.
Available in both Verilog and VHDL.
Applications include any circuit containing a
1-Wire communication bus.
Customer ASIC
Internal
Data Bus
1-Wire
Master
1-Wire
Bus
Interrupt
DESCRIPTION
As more 1-Wire devices become available, more and more users have to deal with the demands of
generating 1-Wire signals to communicate to them. This usually requires “bit-banging” a port pin on a
microprocessor, and having the microprocessor perform the timing functions required for the 1-Wire
protocol. While 1-Wire transmission can be interrupted mid-byte, it cannot be interrupted during the
“low” time of a bit time slot; this means that a CPU will be idled for up to 60 microseconds for each bit
sent and at least 480 microseconds when generating a 1-Wire reset. The 1-Wire Master helps users handle
communication to 1-Wire devices in their system without tying up valuable CPU cycles. Integrated into a
user’s ASIC as a 1-Wire port, the core is available in both VHDL and Verilog code and uses very little
chip area (1492 gates plus 1 bond pad for the Verilog version).
This circuit is designed to be memory mapped into the user’s system and provides complete control of the
1-Wire bus through 8 bit commands. The host CPU loads commands, reads and writes data, and sets
interrupt control through five individual registers. All of the timing and control of the 1-Wire bus are
generated within. The host merely needs to load a command or data and then may go on about its
business. When bus activity has generated a response that the CPU needs to receive, the 1-Wire Master
sets a status bit and, if enabled, generates an interrupt to the CPU. In addition to write and read
simplification, the 1-Wire Master also provides a Search ROM Accelerator function relieving the CPU
from having to perform any single-bit operations on the 1-Wire bus.
1-Wire is a registered trademark of Dallas Semiconductor.
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DS1WM
The operation of the 1-Wire bus is described in detail in the
Book of iButton Standards
[1]; therefore, the
details of that will not be discussed in this document. Each slave device, in general, has its own set of
commands that are described in detail in that device’s data sheet. The user is referred to those documents
for detail on specific slave implementations.
BLOCK DIAGRAM
INTR
INTERRUPT REGISTER
DATA BUS
BUFFER
INT ENABLE REGISTER
INTERRUPT
CONTROL
LOGIC
D0-D7
A0
A1
A2
ADS
RD
WR
EN
CONTROL
LOGIC
COMMAND REGISTER
TRANSMIT BUFFER
1-WIRE
TIMING
AND
CONTROL
DQ
Tx SHIFT REGISTER
Rx SHIFT REGISTER
RECEIVE BUFFER
MASTER
RESET
CLOCK DIV REGISTER
MR
CLK
CLOCK
DIVIDER
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DS1WM
PIN DESCRIPTIONS
The following describes the function of all the block I/O pins. In the following descriptions, 0 represents
logic low and 1 represents logic high.
A0, A1, A2,
Register Select: Address signals connected to these three inputs select a register for the CPU
to read from or write to during data transfer. A table of registers and their addresses is shown below.
Register Addresses
A2
0
0
0
0
1
A1
0
0
1
1
0
A0
0
1
0
1
0
Register
Command Register (read/write)
Transmit Buffer (write), Receive Buffer (read)
Interrupt Register (read)
Interrupt Enable Register (read/write)
Clock Divisor Register (read/write)
ADS
, Address Strobe: The positive edge of an active Address Strobe (
ADS
) signal latches the Register
Select (A0, A1, A2) into an internal latch. Provided that setup and hold timings are observed,
ADS
may
be tied low making the latch transparent.
CLK,
Clock Input: This is a (preferably) 50% duty cycle clock that can range from 3.2MHz to 128MHz.
This clock provides the timing for the 1-Wire bus.
D7-D0,
Data Bus: This bus comprises eight input/output lines. The bus provides bi-directional
communications between the 1-Wire Master and the CPU. Data, control words, and status information are
transferred via this D7-D0 Data Bus.
DQ,
1-Wire Data Line: This open-drain line is the 1-Wire bi-directional data bus. 1-Wire slave devices
are connected to this pin. This pin must be pulled high by an external resistor, nominally 5K
W
.
EN
, Enable: When EN is low, the 1-Wire Master is enabled; this signal acts as the device chip enable.
This enables communication between the 1-Wire Master and the CPU.
INTR,
Interrupt: This line goes to its active state whenever any one of the interrupt types has an active
high condition and is enabled via the Interrupt Enable Register. The INTR signal is reset to an inactive
state when the Interrupt Register is read.
MR,
Master Reset: When this input is high, it clears all the registers and the control logic of the 1-Wire
Master, and sets INTR to its default inactive state, which is HIGH.
RD
, Read: This pin drives the bus during a read cycle. When the circuit is enabled, the CPU can read
status information or data from the selected register by driving
RD
low.
RD
and WR should never be
low simultaneously; if they are, WR takes precedence.
WR
, Write: This pin drives the bus during a write cycle. When WR is low while the circuit is enabled,
the CPU can write control words or data into the selected register.
RD
and WR should never be low
simultaneously; if they are, WR takes precedence.
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DS1WM
OPERATION – CLOCK DIVISOR
All 1-Wire timing patterns are generated using a base clock of 1.0MHz. The 1-Wire Master will generate
this clock frequency internally given an external reference on the CLK pin. The external clock must have
a frequency from 3.2MHz to 128MHz and a 50% duty cycle is preferred. The Clock Divisor Register
controls the internal clock divider and provides the desired reference frequency. This is done in two
stages: first a prescaler divides by 1, 3, 5, or 7, then the remaining circuitry divides by 2, 4, 8, 16, 32,
64,or 128.
Clock Divisor Register
Addr. 04h
X
MSB
X
X
DIV2
DIV1
DIV0
PRE1
PRE0
LSB
The clock divisor must be configured before communication on the 1-Wire bus can take place. This
register is set to 0x00h if a Master Reset occurs. Use the table below to find the proper register value
based on the CLK reference frequency. For example, the user would write 0x10h to this location when
providing a 15MHz input clock.
Clock Divisor Register Settings for Input Clock Rates
Min CLK
Frequency
(MHz)
>3.2
>4.0
>5.0
>6.0
>7.0
>8.0
>10.0
>12.0
>14.0
>16.0
>20.0
>24.0
>28.0
>32.0
>40.0
>48.0
>56.0
>64.0
>80.0
>96.0
>112.0
Max CLK
Frequency
(MHz)
4.0
5.0
6.0
7.0
8.0
10.0
12.0
14.0
16.0
20.0
24.0
28.0
32.0
40.0
48.0
56.0
64.0
80.0
96.0
112.0
128.0
Divider
Ratio
4
5
6
7
8
10
12
14
16
20
24
28
32
40
48
56
64
80
96
112
128
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
1
1
1
1
1
DIV3
1
0
0
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
DIV2
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
DIV1
PRE1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
PRE0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
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DS1WM
OPERATION — TRANSMITTING / RECEIVING DATA
Data sent and received from the 1-Wire Master passes through the transmit/receive buffer location. The 1-
Wire Master is actually double buffered with separate transmit and receive buffers. Writing to this
location connects the Transmit Buffer to the data bus, while reading connects the Receive Buffer to the
data bus.
Transmit Buffer (Write) / Receive Buffer (Read)
Addr. 01h
Data7
MSB
Data6
Data5
Data4
Data3
Data2
Data1
Data0
LSB
Writing a Byte
To send a byte on the 1-Wire bus, the user writes the desired data to the Transmit Buffer. The data is then
moved to the Transmit Shift Register where it is shifted serially onto the bus LSB first. A new byte of
data can then be written to the Transmit Buffer. As soon as the Transmit Shift Register is empty, the data
will be transferred from the Transmit Buffer and the process repeats. Each of these registers has a flag
that may be used as an interrupt source. The Transmit Buffer Empty (TBE) flag is set when the Transmit
Buffer is empty and ready to accept a new byte. As soon as a byte is written into the Transmit Buffer,
TBE is cleared. The Transmit Shift Register Empty (TEMT) flag is set when the shift register has no data
in it and is ready to accept a new byte. As soon as a byte of data is transferred from the Transmit Buffer,
TEMT is cleared and TBE is set. Remember that proper 1-Wire protocol requires a reset before any bus
communication.
Reading a byte
To read data from a slave device, the device must first be ready to transmit data depending on commands
already received from the CPU. Data is retrieved from the bus in a similar fashion to a write operation.
The host initiates a read by writing to the Transmit Buffer. The data that is then shifted into the Receive
Shift Register is the wired-AND of the written data and the data from the slave device. Therefore, in order
to read a byte from a slave device the host must write 0xFFh. When the Receive Shift Register is full the
data is transferred to the Receive Buffer where it can be accessed by the host. Additional bytes can now
be read by sending 0xFFh again. If the slave device is not ready to transmit, the data received will be
identical to that which was transmitted. The Receive Buffer Register can also generate interrupts. The
Receive Buffer flag (RBF) is set when data is transferred from the Receive Shift Register and cleared
when the host reads the register. If RBF is set, no further transmissions should be made on the 1-Wire bus
or else data may be lost, as the byte in the Receive Buffer will be overwritten by the next received byte.
See the timing diagrams for details of the byte reception operation. Generating a 1-Wire reset on the bus
is covered under Command Operations. Interrupt flags are explained in further detail under Interrupt
Operations. Write and read operations are detailed in the timing diagrams.
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