Features ................................................................................................................................................................ 6
Configuring the FFT Compiler............................................................................................................................. 10
Number of Points ....................................................................................................................................... 10
Output Order .............................................................................................................................................. 10
Signal Descriptions ............................................................................................................................................. 11
Interfacing with the FFT Compiler ....................................................................................................................... 12
Number of Points ....................................................................................................................................... 17
Output Order .............................................................................................................................................. 18
Data Width ................................................................................................................................................. 18
Memory Type ............................................................................................................................................. 19
Synthesis and Simulation Tools Tab................................................................................................................... 20
Support Synplify ......................................................................................................................................... 20
Support Precision....................................................................................................................................... 20
Support ModelSim...................................................................................................................................... 20
Support ALDEC.......................................................................................................................................... 20
Chapter 4. IP Core Generation............................................................................................................. 21
Licensing the IP Core.......................................................................................................................................... 21
Getting Started .................................................................................................................................................... 21
IPexpress-Created Files and Top Level Directory Structure............................................................................... 24
Instantiating the Core .......................................................................................................................................... 25
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG54_01.9, August 2011
2
FFT Compiler IP Core User’s Guide
Lattice Semiconductor
Table of Contents
Updating/Regenerating the IP Core .................................................................................................................... 27
Regenerating an IP Core in Diamond ........................................................................................................ 27
Regenerating an IP Core in ispLEVER ...................................................................................................... 27
Chapter 5. Support Resources ............................................................................................................ 29
Telephone Support Hotline ........................................................................................................................ 29
E-mail Support ........................................................................................................................................... 29
Local Support ............................................................................................................................................. 29
Internet ....................................................................................................................................................... 29
Revision History .................................................................................................................................................. 30
Appendix A. Resource Utilization ....................................................................................................... 31
Ordering Part Number................................................................................................................................ 31
Ordering Part Number................................................................................................................................ 32
Ordering Part Number................................................................................................................................ 32
Ordering Part Number................................................................................................................................ 32
Ordering Part Number................................................................................................................................ 33
IPUG54_01.9, August 2011
3
FFT Compiler IP Core User’s Guide
Chapter 1:
Introduction
Lattice's Fast Fourier transform (FFT) Compiler intellectual property (IP) core offers forward and inverse Fast Fou-
rier Transforms for point sizes from 64 to 16384. The FFT Compiler IP core can be configured to perform forward
FFT, inverse FFT (IFFT) or port selectable forward/inverse FFT. The FFT Compiler IP core offers two choices of
implementation: high performance (Streaming I/O) and low resource (Burst I/O). In the high performance imple-
mentation, the FFT Compiler IP core can perform real-time computations with continuous data streaming in and
out at clock rate. There can also be arbitrary gaps between data blocks allowing discontinuous data blocks. The low
resource implementation can be used when it is required to use less slice (logic unit of Lattice FPGA devices) and
Embedded Block RAM (EBR) and Digital Signal Processor (DSP) resources or if the device is too small to accom-
modate the high performance version.
To account for the data growth in fine register length implementations, the FFT Compiler IP core allows several dif-
ferent modes (fixed and dynamic) for scaling data after each radix-2 stage of the FFT computation. The low
resource version also supports block floating point arithmetic that provides increased dynamic range for intermedi-
ate computations. The FFT Compiler IP core also allows the number of FFT points to be varied dynamically
through a port.
Quick Facts
Table 1-1
through
Table 1-5
give quick facts about the FFT Compiler IP core for LatticeECP™, LattceECP2™,
LatticeECP2M™, LatticeECP3™, and LatticeXP2™ devices, respectively.
Table 1-1. FFT Compiler IP Core for LatticeECP Devices Quick Facts
FFT IP Configuration
High performance
256 points
High performance
1024 points
Low performance
256 points
Low performance
256 points
Core
Requirements
FPGA Families Supported
Minimal Device Needed
Targeted Device
Data Path Width
16
2100
3
1700
6
LUTs
sysMEM EBRs
Registers
MULT18X18ADDSUB
Lattice Implementation
Synthesis
Simulation
16
2700
5
2100
8
LatticeECP
LFECP6E
LFECP33E-5F672C
16
800
3
800
2
16
1000
5
900
2
Resource
Utilization
Lattice Diamond
®
1.0 or ispLEVER
®
8.1
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Mentor Graphics ModelSim SE 6.3F
Design Tool
Support
IPUG54_01.9, August 2011
4
FFT Compiler IP Core User’s Guide
Lattice Semiconductor
Introduction
Table 1-2. FFT Compiler IP Core for LatticeECP 2Devices Quick Facts
FFT IP Configuration
High perfor-
mance 256 points
High performance
1024 points
Low performance
256 points
Low performance
256 points
Core
Requirements
FPGA Families Supported
Minimal Device Needed
Targeted Device
Data Path Width
16
2100
3
1700
6
LUTs
sysMEM EBRs
Registers
MULT18X18ADDSUB
Lattice Implementation
Synthesis
Simulation
LFE2-6E
Lattice ECP2
LFE2-12E
16
2700
6
2100
8
LFE2-6E
16
800
3
800
2
LFE2-6E
16
900
3
800
2
LFE2-50E-7F672C
Resource
Utilization
Diamond 1.0 or ispLEVER 8.1
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Mentor Graphics ModelSim SE 6.3F
Design Tool
Support
Table 1-3. FFT Compiler IP Core for LatticeECP2M Devices Quick Facts
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