AD9858-PCBZ datasheet, PDF - EEWORLD Datasheet

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AD9858-PCBZ: DescriptionData Acquisition ADCs/DACs - Specialized 1 GSPS Direct Digital Synthesizer; CategoryDevelopment board/suite/development tools; File Size696KB，34 Pages; ManufacturerADI; Websitehttps://www.analog.com

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Data Acquisition ADCs/DACs - Specialized 1 GSPS Direct Digital Synthesizer

AD9858-PCBZ Parametric

Parameter Name	Attribute value
Product Category	Data Conversion IC Development Tools
Manufacturer	ADI
RoHS	Details
Product	Evaluation Boards
Type	DAC
Tool Is For Evaluation Of	AD9858
Operating Supply Voltage	5 V
Packaging	Bulk
Description/Function	Direct digital synthesizer DAC output evaluation board
Interface Type	Parallel
Maximum Operating Temperature	+ 85 C
Minimum Operating Temperature	- 40 C
Factory Pack Quantity	1
Unit Weight	10.640003 oz

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1 GSPS Direct Digital Synthesizer

AD9858

FEATURES

1 GSPS internal clock speed

Up to 2 GHz input clock (selectable divide-by-2)

Integrated 10-bit DAC

Excellent phase noise and SFDR

32-bit programmable frequency register

Simplified 8-bit parallel and SPI serial control interface

Automatic frequency sweeping capability

4 frequency profiles

3.3 V power supply

Power dissipation: 2 W typical

Integrated programmable charge pump and phase

frequency detector with fast lock circuit

Isolated charge pump supply up to 5 V

Integrated 2 GHz mixer

GENERAL DESCRIPTION

The AD9858 is a direct digital synthesizer (DDS) featuring a

10-bit digital-to-analog converter (DAC) operating up to 1 GSPS.

The AD9858 uses advanced DDS technology coupled with an

internal high speed, high performance DAC to form a digitally

programmable, complete high frequency synthesizer capable of

generating a frequency-agile analog output sine wave at up to

400 MHz. The AD9858 is designed to provide fast frequency

hopping and fine tuning resolution (32-bit frequency tuning

word). The frequency tuning and control words are loaded into

the AD9858 via parallel (8-bit) or serial loading formats. The

AD9858 contains an integrated charge pump (CP) and phase

frequency detector (PFD) for synthesis applications requiring

the combination of a high speed DDS along with phase-locked

loop (PLL) functions. An analog mixer is also provided on chip

for applications requiring the combination of a DDS, PLL, and

mixer, such as frequency translation loops and tuners. The AD9858

also features a divide-by-2 on the clock input, allowing the external

reference clock to be as high as 2 GHz.

The AD9858 is specified to operate over the extended industrial

temperature range of –40°C to +85°C.

APPLICATIONS

VHF/UHF LO synthesis

Tuners

Instrumentation

Agile clock synthesis

Cellular base station hopping synthesizers

Radars

SONET/SDH clock synthesis

LO LO

DIV

CPISET

÷M

÷N

CHARGE

PUMP

PHASE

DETECTOR

IF IF

FUNCTIONAL BLOCK DIAGRAM

RF RF

AD9858

DIGITAL PLL

ANALOG

MULTIPLIER

PHASE ACCUMULATOR

PHASE-TO-

AMPLITUDE

CONVERSION

FREQUENCY ACCUMULATOR

DACISET

DAC

IOUT

FREQUENCY

ACCUMULATOR

RESET

PHASE

ACCUMULATOR

RESET

DELTA

FREQUENCY

RAMP RATE

DELTA

FREQUENCY

WORD

FREQUENCY

TUNING

WORD

PHASE

OFFSET

ADJUST

SYSCLK

RESET

CONTROL REGISTERS

TIMING AND CONTROL LOGIC

FUD

÷8

SYNCLK

REFCLK

03166-001

SYNC

POWER-

DOWN

LOGIC

÷2

PS0 PS1

I/O PORT

(SER/PAR)

Figure 1.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD9858

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Electrical Specifications ................................................................... 3

Absolute Maximum Ratings............................................................ 6

Thermal Performance .................................................................. 6

Explanation of Test Levels ........................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 14

Component Blocks ..................................................................... 14

Modes of Operation ................................................................... 16

Synchronization .......................................................................... 18

Programming the AD9858........................................................ 19

Other Registers ........................................................................... 25

User Profile Registers ................................................................. 25

Applications Information .............................................................. 27

Evaluation Boards ...................................................................... 28

Outline Dimensions ....................................................................... 29

Warning ....................................................................................... 29

Ordering Guide .......................................................................... 29

REVISION HISTORY

2/09—Rev. B to Rev. C

Changes to Features Section, General Description Section, and

Figure 1 .............................................................................................. 1

Changes to Table 1 ............................................................................ 3

Changes to Table 2 ............................................................................ 6

Added Thermal Performance Section ........................................... 6

Changes to Figure 3, Figure 4, and Figure 5.................................. 9

Changes to Figure 9, Figure 10 Caption, Figure 11 Caption,

Figure 13, and Figure 14 ................................................................ 10

Changes to Figure 17 ...................................................................... 11

Changes to Theory of Operation Section and DAC Output

Section .............................................................................................. 14

Changes to Charge Pump Section ................................................ 15

Changes to Modes of Operation Section ..................................... 16

Changes to Single-Tone Mode Section and Frequency Sweeping

Mode Section................................................................................... 17

Changes to SYNCLK and FUD Pins Section and Figure 33 ..... 18

Changes to I/O Port Functionality Section, Parallel

Programming Mode Section, and Figure 35 ............................... 20

Changes to Figure 36 and Serial Programming

Mode Section................................................................................... 21

Changes to Table 6 .......................................................................... 22

Changes to Control Function Register (CFR) Section .............. 23

Changes to CFR[21]: Load Delta Frequency Timer Section .... 24

Changed CFR[14]: Sine/Cosine Select Bit Section to CFR[14]:

Enable Sine Output Bit Section..................................................... 24

Changes to Delta Frequency Tuning Word (DFTW) Section,

Delta Frequency Ramp Rate Word (DFRRW) Section, and

Phase Offset Control Section ........................................................ 25

Changes to Profile Selection Section ........................................... 26

Deleted Frequency Tuning Control Section ............................... 27

Changed AD9858 Application Suggestions Section to

Applications Information Section ................................................ 27

Changes to Table 13 ....................................................................... 28

Added Exposed Paddle Notation to Outline Dimensions ........ 29

4/07—Rev. A to Rev. B

Changed EPAD to TQFP_EP............................................ Universal

Updated Outline Dimensions ....................................................... 31

11/03—Rev. 0 to Rev. A

Changes to Specifications .................................................................5

Moved ESD Caution to .....................................................................6

Moved Pin Configuration to ............................................................7

Moved Pin Function Description to ...............................................8

Changes to Equations .................................................................... 19

Changes to Delta Frequency Ramp Rate Word (DFRRW) ....... 27

4/03—Revision 0: Initial Version

Rev. C | Page 2 of 32

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