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GE28F640W18BD80

Description
Intel㈢ Wireless Flash Memory
Categorystorage    storage   
File Size1MB,100 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
Download Datasheet Parametric View All

GE28F640W18BD80 Overview

Intel㈢ Wireless Flash Memory

GE28F640W18BD80 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIntel
Parts packaging codeBGA
package instructionVFBGA, BGA56,7X8,30
Contacts56
Reach Compliance Codecompli
ECCN code3A991.B.1.A
Maximum access time80 ns
Other featuresSYNCHRONOUS BURST MODE OPERATION ALSO POSSIBLE
startup blockBOTTOM
command user interfaceYES
Universal Flash InterfaceYES
Data pollingNO
JESD-30 codeR-PBGA-B56
JESD-609 codee0
length9 mm
memory density67108864 bi
Memory IC TypeFLASH
memory width16
Number of functions1
Number of departments/size8,127
Number of terminals56
word count4194304 words
character code4000000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize4MX16
Package body materialPLASTIC/EPOXY
encapsulated codeVFBGA
Encapsulate equivalent codeBGA56,7X8,30
Package shapeRECTANGULAR
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
page size4 words
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
power supply1.5/1.8,1.8 V
Programming voltage1.8 V
Certification statusNot Qualified
Maximum seat height1 mm
Department size4K,32K
Maximum standby current0.000005 A
Maximum slew rate0.04 mA
Maximum supply voltage (Vsup)1.95 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formBALL
Terminal pitch0.75 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
switch bitNO
typeNOR TYPE
width7.7 mm
Intel
®
Wireless Flash Memory (W18)
28F320W18, 28F640W18, 28F128W18
Datasheet
Product Features
High Performance Read-While-Write/
Erase
— Burst frequency at 66 MHz
— 60 ns Initial Access Read Speed
— 11 ns Burst-Mode Read Speed
— 20 ns Page-Mode Read Speed
— 4-, 8-, 16-, and Continuous-Word Burst
Mode Reads
— Burst and Page Mode Reads in all
Blocks, across all partition boundaries
— Burst Suspend Feature
— Enhanced Factory Programming at
3.1 µs/word (typ.for 0.13 µm)
Security
— 128-bit Protection Register
— 64-bits Unique Programmed by Intel
— 64-bits User-Programmable
— Absolute Write Protection with V
PP
at
Ground
— Individual and Instantaneous Block
Locking/Unlocking with Lock-Down
Capability
Quality and Reliability
— Temperature Range: –40 °C to +85 °C
— 100k Erase Cycles per Block
— 0.13 µm ETOX™ VIII Process
— 0.18 µm ETOX™ VII Process
Architecture
— Multiple 4-Mbit Partitions
— Dual Operation: RWW or RWE
— 8KB parameter blocks
— 64KB main blocks
— Top or Bottom Parameter Devices
— 16-bit wide data bus
Software
— 5 µs (typ.) Program and Erase Suspend
Latency Time
— Flash Data Integrator (FDI) and Common
Flash Interface (CFI) Compatible
— Programmable WAIT Signal Polarity
Packaging and Power
— 0.13 µm: 32-, 64-, and 128-Mbit in VF
BGA Package; 128-Mbit in QUAD+
Package
— 0.18 µm: 32- and 128-Mbit Densities in
VF BGA Package; 64-Mbit Density in
µBGA* Package
— 56 Active Ball Matrix, 0.75 mm Ball-
Pitch
— V
CC
= 1.70 V to 1.95 V
— V
CCQ
= 1.70 V to 2.24 V or 1.35 V to
1.80 V
— Standby current (0.13 µm): 8µA (typ.)
— Read current: 7mA (typ.)
The Intel
®
Wireless Flash Memory (W18) device with flexible multi-partition dual operation,
provides high-performance asynchronous and synchronous burst reads. It is an ideal memory for
low-voltage burst CPUs. Combining high read performance with flash memory’s intrinsic non-
volatility, the W18 device eliminates the traditional system-performance paradigm of shadowing
redundant code memory from slow nonvolatile storage to faster execution memory. It reduces
the total memory requirement that increases reliability and reduces overall system power
consumption and cost.
The W18 device’s flexible multi-partition architecture allows programming or erasing to occur
in one partition while reading from another partition. This allows for higher data write
throughput compared to single partition architectures. The dual-operation architecture also
allows two processors to interleave code operations while program and erase operations take
place in the background. The designer can also choose the size of the code and data partitions via
the flexible multi-partition architecture.
Notice:
This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the
latest datasheet before finalizing a design.
290701-009
December 2003
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