Features .............................................................................................................................................................. 10
PCI Target Control ..................................................................................................................................... 12
Local Master Interface Control ................................................................................................................... 12
Local Target Control................................................................................................................................... 13
Parity Generator and Checker ................................................................................................................... 13
Signal Descriptions ............................................................................................................................................. 13
Local Interface Signals............................................................................................................................... 15
PCI Configuration Space Setup .......................................................................................................................... 18
Status Register........................................................................................................................................... 21
Base Address Registers............................................................................................................................. 22
BAR Mapped to Memory Space................................................................................................................. 22
Bar Mapped to I/O Space........................................................................................................................... 23
Cache Line Size ......................................................................................................................................... 23
Subsystem Vendor ID ................................................................................................................................ 23
Interrupt Line .............................................................................................................................................. 24
PCI Configuration Using Core Configuration Space Port........................................................................... 25
Local Bus Interface ............................................................................................................................................. 30
Fast Back-to-Back Transactions ................................................................................................................ 76
Master and Target Termination........................................................................................................................... 81
Basic PCI Target Read and Write Transactions ................................................................................................. 81
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG18_09.2, November 2010
2
PCI IP Core User’s Guide
Lattice Semiconductor
Table of Contents
32-bit PCI Target with a 32-bit Local Bus Memory Transactions ............................................................... 82
64-Bit PCI Target with a 64-Bit Local Bus.................................................................................................. 87
32-Bit PCI Target with a 64-Bit Local Bus.................................................................................................. 90
Configuration Read and Write Transactions .............................................................................................. 94
PCI Target I/O Read and Write Transactions ............................................................................................ 96
Disconnect With Data............................................................................................................................... 124
Disconnect Without Data.......................................................................................................................... 127
Bus Tab............................................................................................................................................................. 137
Bus Definition ........................................................................................................................................... 137
Vendor ID [15:0] ....................................................................................................................................... 139
Device ID [15:0]........................................................................................................................................ 139
Subsystem Vendor ID [15:0] .................................................................................................................... 139
Subsystem ID [15:0]................................................................................................................................. 139
Revision ID [15:0]..................................................................................................................................... 139
Class Code (Base Class, Bus Class, Interface)....................................................................................... 139
Base Address Registers........................................................................................................................... 142
BAR Configuration Options ............................................................................................................................... 142
BAR Width................................................................................................................................................ 142
BAR Type................................................................................................................................................. 142
Address Space Size................................................................................................................................. 142
Chapter 4. IP Core Generation........................................................................................................... 143
Licensing the IP Core........................................................................................................................................ 143
Getting Started .................................................................................................................................................. 143
IPexpress-Created Files and Top Level Directory Structure............................................................................. 146
Instantiating the Core ........................................................................................................................................ 147
Enabling Hardware Evaluation in Diamond.............................................................................................. 148
Enabling Hardware Evaluation in ispLEVER............................................................................................ 149
Updating/Regenerating the IP Core .................................................................................................................. 149
IPUG18_09.2, November 2010
3
PCI IP Core User’s Guide
Lattice Semiconductor
Table of Contents
Regenerating an IP Core in Diamond ...................................................................................................... 149
Regenerating an IP Core in ispLEVER .................................................................................................... 149
Chapter 5. Support Resources .......................................................................................................... 151
Telephone Support Hotline ...................................................................................................................... 151
E-mail Support ......................................................................................................................................... 151
Local Support ........................................................................................................................................... 151
Internet ..................................................................................................................................................... 151
Revision History ................................................................................................................................................ 152
Appendix A. Resource Utilization ..................................................................................................... 153
LatticeECP and LatticeEC FPGAs .................................................................................................................... 153
Ordering Part Number.............................................................................................................................. 153
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