Data Sheet
FEATURES
14-Bit, 170 MSPS/250 MSPS, JESD204B,
Dual Analog-to-Digital Converter
AD9250
FUNCTIONAL BLOCK DIAGRAM
AVDD DRVDD
DVDD
AGND DGND DRGND
JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and
250 MSPS
Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz
AIN and 250 MSPS
Total power consumption: 711 mW at 250 MSPS
1.8 V supply voltages
Integer 1-to-8 input clock divider
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal analog-to-digital converter (ADC) voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer (DCS)
95 dB channel isolation/crosstalk
Serial port control
Energy saving power-down modes
AD9250
VIN+A
VIN–A
VCM
VIN+B
VIN–B
PIPELINE
14-BIT ADC
PIPELINE
14-BIT ADC
JESD204B
INTERFACE
HIGH
SPEED
SERIALIZERS
CML, TX
OUTPUTS
SERDOUT1±
SERDOUT0±
CONTROL
REGISTERS
SYSREF±
SYNCINB±
CLK±
RFCLK
CMOS
DIGITAL
INPUT
PDWN
CLOCK
GENERATION
CMOS
DIGITAL
INPUT/OUTPUT
FAST
DETECT
CMOS
DIGITAL
OUTPUT
FDA
FDB
RST
SDIO SCLK
CS
Figure 1.
PRODUCT HIGHLIGHTS
1. Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
2. The configurable JESD204B output block supports up to
5 Gbps per lane.
3. An on-chip, phase-locked loop (PLL) allows users to provide
a single ADC sampling clock; the PLL multiplies the ADC
sampling clock to produce the corresponding JESD204B
data rate clock.
4. Support for an optional RF clock input to ease system board
design.
5. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
6. Operation from a single 1.8 V power supply.
7. Standard serial port interface (SPI) that supports various
product features and functions such as controlling the clock
DCS, power-down, test modes, voltage reference mode, over
range fast detection, and serial output configuration.
APPLICATIONS
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
I/Q demodulation systems
Smart antenna systems
Electronic test and measurement equipment
Radar receivers
COMSEC radio architectures
IED detection/jamming systems
General-purpose software radios
Broadband data applications
This product may be protected by one or more U.S. or international patents.
Rev. E
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Trademarks and registered trademarks are the property of their respective owners.
10559-001
AD9250
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications..................................................................................... 5
ADC DC Specifications ............................................................... 5
ADC AC Specifications ............................................................... 6
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 9
Timing Specifications ................................................................ 10
Absolute Maximum Ratings .......................................................... 11
Thermal Characteristics ............................................................ 11
ESD Caution ................................................................................ 11
Pin Configuration and Function Descriptions ........................... 12
Typical Performance Characteristics ........................................... 14
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 20
ADC Architecture ...................................................................... 20
Analog Input Considerations.................................................... 20
Voltage Reference ....................................................................... 21
Clock Input Considerations ...................................................... 21
Power Dissipation and Standby Mode ..................................... 24
Digital Outputs ............................................................................... 25
JESD204B Transmit Top Level Description ............................ 25
Data Sheet
JESD204B Overview .................................................................. 25
JESD204B Synchronization Details ......................................... 26
Link Setup Parameters ............................................................... 26
Frame and Lane Alignment Monitoring and Correction ..... 30
Digital Outputs and Timing ..................................................... 30
ADC Overrange and Gain Control.......................................... 32
ADC Overrange (OR)................................................................ 32
Gain Switching ............................................................................ 32
DC Correction ................................................................................ 33
DC Correction Bandwidth........................................................ 33
DC Correction Readback .......................................................... 33
DC Correction Freeze ................................................................ 33
DC Correction (DCC) Enable Bits .......................................... 33
Serial Port Interface (SPI) .............................................................. 34
Configuration Using the SPI ..................................................... 34
Hardware Interface ..................................................................... 34
SPI Accessible Features .............................................................. 35
Memory Map .................................................................................. 36
Reading the Memory Map Register Table............................... 36
Memory Map Register Table ..................................................... 37
Memory Map Register Description ......................................... 41
Applications Information .............................................................. 42
Design Guidelines ...................................................................... 42
SPI Initialization Sequence ....................................................... 42
Outline Dimensions ....................................................................... 45
Ordering Guide .......................................................................... 45
Rev. E | Page 2 of 45
Data Sheet
REVISION HISTORY
9/2017—Rev. D to Rev. E
Changes to Channel-Specific Registers Section ................................. 36
Changes to Table 18 ................................................................................... 37
Changes to Figure 63 and Table 19 ........................................................ 43
5/2017—Rev. C to Rev. D
Change to Differential Output Voltage (V
OD
) Parameter, Table 3 .... 8
Deleted Synchronization Section ..................................................26
Changes to Link Setup Parameters Section .................................26
Deleted Clock Adjustment Register Writes Section ...................27
Added Internal FIFO Timing Optimization Section .................28
Changes to Table 14 ........................................................................30
Changes to Channel-Specific Registers Section ..........................36
Deleted Transfer Register Map Section ........................................37
Changes to Table 18 ........................................................................37
Added SPI Initialization Sequence Section..................................42
Added Figure 63 and Table 19; Renumbered Sequentially ........43
Deleted JESD204B Configuration Section ...................................44
Updated Outline Dimensions ........................................................45
1/2016—Rev. B to Rev. C
Moved Revision History Section ..................................................... 3
Changes to Nyquist Clock Input Options ....................................22
Added Synchronization Section ....................................................26
Added Click Adjustment Register Writes Section ......................27
Changes to Link Setup Parameters Section .................................27
Change to Additional Digital Output Configuration Options
Section ..............................................................................................29
Added Table 14, Renumbered Sequentially .................................30
Changes to Table 18 ........................................................................38
Added JESD204B Configuration Section ....................................43
AD9250
12/2013—Rev. A to Rev. B
Change to Features Section .............................................................. 1
Change to Functional Block Diagram ............................................ 1
Change to SYNCIN Input (SYNCINB+/SYNCINB−), Logic
Compliance Parameter, Table 3 ....................................................... 6
Changes to Data Output Parameters, Table 4 ............................... 8
Changes to Figure 3 .......................................................................... 9
Change to Figure 30, Added Figure 34 through Figure 37;
Renumbered Sequentially .............................................................. 17
Changes to Table 9 .......................................................................... 20
Change to Figure 47 ........................................................................ 21
Changes to JESD204B Overview Section .................................... 24
Change to Configure Details Options Section ............................ 26
Change to Check FCHK, Checksum of JESD204B Interface
Parameters Section .......................................................................... 27
Changes to Figure 54 ...................................................................... 28
Changes to Figure 57 and Figure 58 ............................................. 29
Changes to Figure 59 and Figure 60 ............................................. 30
Changes to Table 17 ........................................................................ 36
Updated Outline Dimensions........................................................ 42
3/2013—Rev. 0 to Rev. A
Changes to High Level Input Current and Low Level Input
Current; Table 3 ................................................................................. 6
Changes to Table 4 ............................................................................ 8
Changes to Figure 3 Caption ........................................................... 9
Changes to Digital Inputs Description; Table 8 .......................... 11
Changes to JESD204B Synchronization Details Section ........... 24
Changes to Configure Detailed Options Section........................ 25
Changes to Fast Threshold Detection (FDA and FDB) Section ...30
Deleted Built-In Self-Test (BIST) and Output Test Section ...... 32
Changes to Transfer Register Map Section .................................. 34
Changes to Table 17 ........................................................................ 35
10/2012—Revision 0: Initial Version
Rev. E | Page 3 of 45
AD9250
GENERAL DESCRIPTION
The
AD9250
is a dual, 14-bit ADC with sampling speeds of up
to 250 MSPS. The
AD9250
is designed to support communications
applications where low cost, small size, wide bandwidth, and
versatility are desired.
The ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC cores feature wide bandwidth inputs supporting a variety
of user-selectable input ranges. An integrated voltage reference
eases design considerations. A duty cycle stabilizer is provided
to compensate for variations in the ADC clock duty cycle, allowing
the converters to maintain excellent performance. The JESD204B
high speed serial interface reduces board routing requirements
and lowers pin count requirements for the receiving device.
Data Sheet
By default, the ADC output data is routed directly to the two
JESD204B serial output lanes. These outputs are at CML voltage
levels. Four modes support any combination of M = 1 or 2 (single
or dual converters) and L = 1 or 2 (one or two lanes). For dual
ADC mode, data can be sent through two lanes at the maximum
sampling rate of 250 MSPS. However, if data is sent through
one lane, a sampling rate of up to 125 MSPS is supported.
Synchronization inputs (SYNCINB± and SYSREF±) are provided.
Flexible power-down options allow significant power savings,
when desired. Programmable overrange level detection is
supported for each channel via the dedicated fast detect pins.
Programming for setup and control are accomplished using a
3-wire SPI-compatible serial interface.
The
AD9250
is available in a 48-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C.
Rev. E | Page 4 of 45
Data Sheet
SPECIFICATIONS
ADC DC SPECIFICATIONS
AD9250
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, duty cycle stabilizer (DCS) enabled, link parameters used were M = 2 and L = 2, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
1
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Min
14
AD9250-170
Typ
Max
Min
14
AD9250-250
Typ
Max
Unit
Bits
Guaranteed
−16
−6
±0.25
±2.1
±1.5
−15
−2
±2
±16
1.49
1.75
2.5
20
0.9
+15
+3.5
−15
−2
+16
+2
±0.75
−16
−6
Guaranteed
+16
+2.5
±0.75
±0.25
±3.5
±1.5
+15
+3
±2
±44
1.49
1.75
2.5
20
0.9
mV
%FSR
LSB
LSB
LSB
LSB
mV
%FSR
ppm/°C
ppm/°C
LSB rms
V p-p
pF
kΩ
V
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span
Input Capacitance
2
Input Resistance
3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
DVDD
Supply Current
I
AVDD
I
DRVDD
+ I
DVDD
POWER CONSUMPTION
Sine Wave Input
Standby Power
4
Power-Down Power
1
2
Full
Full
Full
Full
Full
Full
Full
Full
1.7
1.7
1.7
1.8
1.8
1.8
233
104
607
280
9
1.9
1.9
1.9
260
113
1.7
1.7
1.7
1.8
1.8
1.8
255
140
711
339
9
1.9
1.9
1.9
280
160
V
V
V
mA
mA
mW
mW
mW
Measured with a low input frequency, full-scale sine wave.
Input capacitance refers to the effective capacitance between one differential input pin and its complement.
3
Input resistance refers to the effective resistance between one differential input pin and its complement.
4
Standby power is measured with a dc input and the CLK± pin active.
Rev. E | Page 5 of 45
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