For f < 10 MHz, use a dc-coupled, CMOS compatible square wave, slew rate >
21 V/µs.
AC-coupled.
CMOS compatible.
REF
IN
Input Capacitance
REF
IN
Input Current
PHASE DETECTOR
Phase Detector Frequency
2
CHARGE PUMP
I
CP
Sink/Source
High Value
Low Value
Absolute Accuracy
R
SET
Range
I
CP
Three-State Leakage Current
Matching
I
CP
vs. V
CP
I
CP
vs. Temperature
LOGIC INPUTS
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
/I
INL
, Input Current
C
IN
, Input Capacitance
LOGIC OUTPUTS
V
OH
, Output High Voltage
V
OL
, Output Low Voltage
POWER SUPPLIES
AV
DD
DV
DD
, SDV
DD
V
P
I
DD3
Low Power Sleep Mode
NOISE CHARACTERISTICS
Phase Noise Figure of Merit
4
ADF4154 Phase Noise Floor
5
Phase Noise Performance
6
1750 MHz Output
7
5
312.5
2.5
1.5/10
1
2
2
2
1.4
0.6
±1
10
1.4
0.4
2.7/3.3
AV
DD
AV
DD
/5.5
24
1
−213
−143
−139
−102
mA typ
µA typ
% typ
kΩ min/max
nA typ
% typ
% typ
% typ
V min
V max
µA max
pF max
V min
V max
V min/V max
V min/V max
mA max
µA typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Programmable. See Table 5.
With R
SET
= 5.1 kΩ.
With R
SET
= 5.1 kΩ.
Sink and source current.
0.5 V < V
CP
< V
P
– 0.5.
0.5 V < V
CP
< V
P
– 0.5.
V
CP
= V
P
/2.
Open-drain 1 kΩ pull-up to 1.8 V.
I
OL
= 500 µA.
20 mA typical.
@ 10 MHz PFD frequency.
@ 26 MHz PFD frequency.
@ VCO output.
@ 1 kHz offset, 26 MHz PFD frequency.
1
2
Use a square wave for frequencies below f
MIN
.
Guaranteed by design. Sample tested to ensure compliance.
3
AC coupling ensures AV
DD
/2 bias. See Figure 17 for typical circuit.
4
This figure can be used to calculate phase noise for any application. Use the formula –213 + 10log(f
PFD
) + 20logN to calculate in-band phase noise performance, as seen
at the VCO output. The value given is the lowest noise mode.
5
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N-divider value).
The value given is the lowest noise mode.
6
The phase noise is measured with the EVAL-ADF4154EB1 evaluation board and the HP8562E spectrum analyzer.
7
f
REFIN
= 26 MHz; f
PFD
= 26 MHz; offset frequency = 1 kHz; RF
OUT
= 1750 MHz; loop B/W = 20 kHz; lowest noise mode.
Rev. 0 | Page 3 of 20
ADF4154
TIMING CHARACTERISTICS
Table 2. AV
DD
= DV
DD
= SDV
DD
= 2.7 V to 3.3 V; V
P
= AV
DD
to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise
noted; dBm referred to 50 Ω.
Parameter
1
t
1
t
2
t
3
t
4
t
5
t
6
t
7
Limit at T
MIN
to T
MAX
(B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE Setup Time
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulse Width
1
Guaranteed by design, but not production tested.
t
4
CLOCK
t
5
t
2
DATA
DB23 (MSB)
DB22
t
3
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
7
LE
t
1
LE
t
6
04833-0-026
Figure 2. Timing Diagram
Rev. 0 | Page 4 of 20
ADF4154
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings.
1, 2, 3
T
A
= 25°C, unless
otherwise noted.
Parameter
V
DD
to GND
V
DD
to V
DD
V
P
to GND
V
P
to V
DD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REF
IN
, RF
IN
to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP θ
JA
Thermal Impedance
LFCSP θ
JA
Thermal Impedance
(Paddle Soldered)
LFCSP θ
JA
Thermal Impedance
(Paddle Not Soldered)
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared
Rating
−0.3 V to +4 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to +5.8 V
−0.3 V to V
DD
+ 0.3 V
−0.3 V to V
DD
+ 0.3 V
−0.3 V to V
DD
+ 0.3 V
−40°C to +85°C
−65°C to +150°C
150°C
150.4°C/W
122°C/W
216°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
This device is a high performance RF integrated circuit with an ESD rating of
< 2 kV, and it is ESD sensitive. Proper precautions should be taken for
handling and assembly.
2
GND = A
GND
= D
GND
= 0 V.
3
V
DD
= AV
DD
= DV
DD
= SDV
DD
.
215°C
220°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
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Test/Measurement
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