LM555 — Single Timer
January 2013
LM555
Single Timer
Features
•
•
•
•
•
High-Current Drive Capability: 200 mA
Adjustable Duty Cycle
Temperature Stability of 0.005%/°C
Timing From
μs
to Hours
Turn off Time Less Than 2
μs
Description
The LM555 is a highly stable controller capable of pro-
ducing accurate timing pulses. With a monostable opera-
tion, the delay is controlled by one external resistor and
one capacitor. With astable operation, the frequency and
duty cycle are accurately controlled by two external
resistors and one capacitor.
8-DIP
Applications
•
•
•
•
Precision Timing
Pulse Generation
Delay Generation
Sequential Timing
1
8-SOIC
1
Ordering Information
Part Number
LM555CN
LM555CM
LM555CMX
0 ~ +70°C
Operating Temperature Range
Top Mark
LM555CN
LM555CM
LM555CM
Package
DIP 8L
SOIC 8L
SOIC 8L
Packing Method
Rail
Rail
Tape & Reel
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
1
LM555 — Single Timer
Block Diagram
R
R
R
8
GND
GND
1
V
CC
Vcc
Comp.
Trigger
Trigger
Discharging Tr.
Discharging Transistor
7
2
Discharge
Discharge
Output
Output
3
OutPut
Stage
F/F
6
Comp.
Threshold
Threshold
Reset
Reset
4
5
V
REF
Vref
Control
Control
Threshold
Voltage
Voltage
Figure 1. Block Diagram
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. Values are at T
A
= 25°C unless otherwise noted.
Symbol
V
CC
T
LEAD
P
D
T
OPR
T
STG
Supply Voltage
Parameter
Lead Temperature (Soldering 10s)
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Value
16
300
600
0 ~ +70
-65 ~ +150
Unit
V
°C
mW
°C
°C
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
2
LM555 — Single Timer
Electrical Characteristics
Values are at T
A
= 25°C, V
CC
= 5 ~ 15 V unless otherwise specified.
Parameter
Supply Voltage
Supply Current (Low Stable)
(1)
Timing Error (Monostable)
Initial Accuracy
(2)
Drift with Temperature
(3)
Drift with Supply Voltage
(3)
Timing Error (Astable)
InItial Accuracy
(2)
Drift with Temperature
(3)
Drift with Supply Voltage
(3)
Control Voltage
Threshold Voltage
Threshold Current
(4)
Trigger Voltage
Trigger Current
Reset Voltage
Reset Current
Low Output Voltage
Symbol
V
CC
I
CC
ACCUR
Δt
/
ΔT
Δt
/
ΔV
CC
ACCUR
Δt
/
ΔT
Δt
/
ΔV
CC
V
C
V
TH
I
TH
V
TR
I
TR
V
RST
I
RST
V
OL
Conditions
V
CC
= 5 V, R
L
=
∞
V
CC
= 15 V, R
L
=
∞
R
A
= 1 kΩ to100 kΩ
C = 0.1
μF
Min.
4.5
Typ.
3
7.5
1.0
50
0.1
2.25
Max.
16.0
6
15.0
3.0
Unit
V
mA
mA
%
ppm / °C
0.5
%/V
%
ppm / °C
%/V
R
A
= 1 kΩ to 100kΩ
C = 0.1
μF
V
CC
= 15 V
V
CC
= 5 V
V
CC
= 15 V
V
CC
= 5V
V
CC
= 5 V
V
CC
= 15 V
V
TR
= 0 V
0.4
I
SINK
= 10 mA
I
SINK
= 50 mA
I
SOURCE
= 200 mA
I
SOURCE
= 100 mA
12.75
2.75
1.10
4.5
9.0
2.60
150
0.3
10.0
3.33
10.0
3.33
0.10
1.67
5.0
0.01
0.7
0.1
0.06
0.30
0.05
12.5
13.30
3.30
100
100
20
100
0.25
2.20
5.6
2.00
1.0
0.4
0.25
0.75
0.35
11.0
4.00
V
V
V
V
μA
V
V
μA
V
mA
V
V
V
V
V
V
ns
ns
nA
V
CC
= 15 V
V
CC
= 5 V, I
SINK
= 5 mA
High Output Voltage
Rise Time of Output
(3)
Fall Time of Output
(3)
V
OH
t
R
t
F
I
LKG
V
CC
= 15 V
V
CC
= 5 V, I
SOURCE
= 100 mA
Discharge Leakage Current
Notes:
1. When the output is high, the supply current is typically 1 mA less than at V
CC
= 5 V.
2. Tested at V
CC
= 5.0 V and V
CC
= 15 V.
3. These parameters, although guaranteed, are not 100% tested in production.
4.
This determines the maximum value of R
A
+ R
B
for 15 V operation, the maximum total R = 20 MΩ, and for 5 V
operation, the maximum total R = 6.7 MΩ.
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
www.fairchildsemi.com
3
LM555 — Single Timer
Application Information
Table 1 below is the basic operating table of 555 timer.
Table 1. Basic Operating Table
Reset
(PIN 4)
Low
High
High
V
TR
(PIN 2)
X
< 1/3 V
CC
> 1/3 V
CC
V
TH
(PIN 6)
X
X
> 2/3 V
CC
Output
(PIN 3)
Low
High
Low
Discharging
Transistor
(PIN 7)
ON
OFF
ON
High
> 1/3 V
CC
< 2/3 V
CC
Previous State
When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold volt-
age or the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes accord-
ing to threshold voltage and trigger voltage.
When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal dis-
charge transistor turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer
output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply volt-
age, the timer's internal discharge transistor turns off, increasing the threshold voltage and driving the timer output
again at high.
1. Monostable Operation
+Vcc
10
2
=1
k
Ω
4
RESET
Trigger
8
Vcc
DISCH
R
A
Capacitance(uF)
10
1
10
0k
Ω
10
k
Ω
Ω
7
6
C1
10
0
2
TRIG
THRES
10
-1
3
R
L
OUT
GND
CONT
5
C2
10
-2
1
10
-3
10
-5
10
-4
R
10
-3
10
-2
10
-1
1M
10
0
10
M
10
1
A
Ω
10
2
Time Delay(s)
Figure2. Monostable Circuit
Figure 3. Resistance and Capacitance vs.
Time Delay (t
D
)
Figure 4. Waveforms of Monostable Operation
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
4
www.fairchildsemi.com
LM555 — Single Timer
1. Monostable Operation
Figure 2 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage
falls below V
CC
/3. When the trigger pulse voltage applied to the #2 pin falls below V
CC
/3 while the timer output is low,
the timer's internal flip-flop turns the discharging transistor off and causes the timer output to become high by charging
the external capacitor C1 and setting the flip-flop output at the same time.
The voltage across the external capacitor C1, V
C1
increases exponentially with the time constant t = R
A
*C and
reaches 2 V
CC
/3 at t
D
= 1.1 R
A
*C. Hence, capacitor C1 is charged through resistor R
A
. The greater the time constant
R
A
C, the longer it takes for the V
C1
to reach 2 V
CC
/3. In other words, the time constant R
A
C controls the output pulse
width.
When the applied voltage to the capacitor C1 reaches 2 V
CC
/3, the comparator on the trigger terminal resets the flip-
flop, turning the discharging transistor on. At this time, C1 begins to discharge and the timer output converts to low.
In this way, the timer operating in the monostable repeats the above process. Figure 3 shows the time constant rela-
tionship based on R
A
and C. Figure 4 shows the general waveforms during the monostable operation.
It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of V
CC
/3 before
the timer output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied
while the output is high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at
the end of the output pulse remains at below V
CC
/3. Figure 5 shows such a timer output abnormality.
Figure 5. Waveforms of Monostable Operation
(abnormal)
2. Astable Operation
+Vcc
100
R
A
(R
A
+2R
B
)
10
Ω
1k
4
RESET
8
Vcc
DISCH
Capacitance(uF)
7
R
B
k
Ω
10
2
TRIG
THRES
6
1
Ω
0k
10
1M
Ω
0.1
M
10
Ω
3
OUT
GND
R
L
CONT
5
C2
C1
0.01
1
1E-3
100m
1
10
100
1k
10k
100k
Frequency(Hz)
Figure 6. A Stable Circuit
Figure 7. Capacitance and Resistance vs. Frequency
© 2002 Fairchild Semiconductor Corporation
LM555 Rev. 1.1.0
5
www.fairchildsemi.com
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