ZXBM2001
ZXBM2002 ZXBM2003
Absolute maximum ratings
Parameter
Supply Voltage
Input Current
Power Dissipation 25°C
Operating Temp.
Storage Temp.
Symbol
V
CCmax
I
CCmax
P
Dmax
T
OPR
T
STG
Limits
-0.6 to 20
200
500
-40 to 85
-55 to 150
Unit
V
mA
mW
C
C
Power Dissipation
1) Maximum allowable Power Dissipation, P
D
,
is shown plotted against Ambient Temperature,
T
A
, in the accompanying Power Derating Curve,
indicating the Safe Operating Area for the device.
2) Power consumed by the device, P
T
, can be
calculated from the equation:
P
T
= P
Q
+ P
Ph
where
P
Q
is power dissipated under quiescent
current conditions, given by:
P
Q
= V
CC
x I
CC
where V
CC
is the application
device Supply Voltage
and
I
CC
is the maximum Supply
Current given in the Electrical
Characteristics
and
P
Ph
is power generated due to either one of
the phase outputs Ph1 or Ph2 being
active, given by:
P
Ph
= I
OL
x V
OL
where
and
I
OL
is the application Ph1 and Ph2
output currents
V
OL
is the maximum Low Level
Output Voltage for the Ph1 and
Ph2 outputs given in the Electrical
Characteristics
ISSUE 4 - OCTOBER 2004
SEMICONDUCTORS
2
ZXBM2001
ZXBM2002 ZXBM2003
Electrical Characteristics
(at T
amb
= 25°C & V
CC
= 12V)
Parameter
Supply Voltage
Supply Current
Hall Amp Input Voltage
Hall Amp Common Mode Voltage
Hall Amp Input Offset
Hall Amp Bias Current
PH1, PH2 Output High
PH1, PH2 Output Off Leakage
Current
PH1, PH2 Output Current High
Lock/FG Maximum Collector
Voltage
Lock/FG Sink Current
Lock/FG Low Level O/P Voltage
C
LCK
Charge Current
C
LCK
Discharge Current
Lock condition On:Off ratio
C
LCK
High Threshold Voltage
C
LCK
Low Threshold Voltage
C
PWM
Charge Current
C
PWM
Discharge Current
PWM Frequency
C
PWM
High Threshold Voltage
C
PWM
Low Threshold Voltage
SPD Voltage Control Range
SPD Open Circuit Voltage
V
THH
V
THL
I
PWMC
I
PWMD
F
PWM
V
THH
V
THL
V
SPD
1
1.5
3.6
50
V
CM
V
OFS
V
BS
V
OH
I
OFF
I
OH
V
OH
I
OL
V
OL
I
LCKC
I
LCKD
1:7
-1.8
0.3
-2.8
0.28
1:10
2.0
1.0
4.3
62
24
34
2.0
1.0
2
5.0
75
V
V
A
A
kHz
kHz
V
V
V
V
2
3
V
in
= 1.5V
V
in
= 1.5V
C
PWM
= 150pF
C
PWM
= 100pF
0.35
V
CC
-2.2
Symbol
V
CC
I
CC
40
0.5
0.5V
CC
±7
-350
V
CC
-1.8
10
-80
V
CC
5
0.5
V
CC
-1.5
Min
4.5
2.2
Typ
Max
18
3.25
Unit
V
mA
mV
V
mV
nA
V
A
mA
V
mA
V
A
A
I
OL
= 5mA
V
in
= 1.5V
V
in
= 1.5V
I
OH
= 80mA
No Load
1
diff p-p
Conditions
Notes:
1
Measured with pins H+, H-, CLCK and CPWM = 0V and all other signal pins open circuit.
2
The 1V minimum represents 100% PWM drive and 2V represents 0% PWM drive.
3
This voltage is determined by an internal resistor network of 52.5k from the pin to Gnd and 19.5k
resistors track each other the absolute values are subject to a ±20% manufacturing tolerance
from the pin to a 2V reference. Whilst both
ISSUE 4 - OCTOBER 2004
3
SEMICONDUCTORS
ZXBM2001
ZXBM2002 ZXBM2003
Block Diagram (ZXBM2001):
Pin Assignments
Top View
Pin Functional Descriptions
1. VCC
- Applied voltage
2. H+
3. H-
- Hall input
- Hall input
This is the device supply voltage. For 5V to 12V fans this
can be supplied directly from the Fan Motor supply. For
fans likely to run in excess of the 18V maximum rating
for the device this will be supplied from an external
regulator such as a zener diode.
The rotor position of the Fan Motor is detected by a Hall
sensor whose output is applied to these pins. This
sensor can be either a 4 pin ‘naked’ Hall device or a 3
pin buffered switching type. For a 4 pin device the
differential Hall output signal is connected to the H+
and H- pins. For a 3 pin buffered Hall sensor the Hall
device output is attached to the H+ pin whilst the H- pin
has an external potential divider attached to hold the
pin at half V
CC
. When H+ is high in relation to H- Ph2 is
the active drive.
ISSUE 4 - OCTOBER 2004
SEMICONDUCTORS
4
ZXBM2001
ZXBM2002 ZXBM2003
4. SPD
- Speed control voltage input
This pin provides control over the Fan Motor speed by
varying the Pulse Width Modulated (PWM) drive ratio
at the Ph1 and Ph2 outputs. This control signal can take
the form of either a voltage input of nominal range 2V
to 1V, representing 0% to 100% drive respectively, or
alternatively a thermistor can be attached to this pin to
control the voltage. A third method of speed control is
available by the application of an externally derived
PWM signal and this will be discussed under the C
PWM
pin.
This pin has an internal potential divider between an
internal 2.0V reference and Gnd (see Block Diagram)
designed to hold the pin at approximately 1.5V. This
will represent a drive of nominally 50% PWM. For
thermal speed control a 100k NTC thermistor is
connected between the SPD and ground will provide a
drive nominally 70% at 25°C and 100% at 50°C. As the
thermistor is connected in parallel with the internal
resistor the non-linearity of an NTC thermistor is
largely taken out. A linearity of typically ±2.5% is
achievable.
Lower values of thermistor can be used if needed and
in this situation an external potential divider will be
needed to set the speed range. This will take the form of
a resistor from the SPD pint to Vcc and a resistor from
the SPD pin to Gnd. Full details are given in the
ZXBM200x series Application Note.
If speed control is not required this pin is can be left
open circuit for 50% drive or tied to ground by a 10k
resistor to provide 100% drive.
If required this pin can also be used as an enable pin.
The application of a voltage of 2.0V to V
CC
will to force
the PWM drive fully off, in effect disabling the drive.
5. GND
- Ground
On the ZXBM2001 the Lock/FG pin is designed to be a
dual function pin to provide an indication of the Fans
rotational speed together with an indication of when
the Fan has failed rotating for whatever reason (Rotor
Locked condition). Under correct operating conditions,
and with the external pull-up in place, this pin will
provide an output signal whose frequency will be twice
that of the rotational frequency of the fan. Should the
fan itself stop rotating for any reason, i.e. an
obstruction in the fan blade or a seized bearing, then
the device will enter a Rotor Locked condition. In this
condition the Lock/FG pin will go high (regardless of
the state of the Hall sensor) when the C
LCK
pin reaches
the V
THH
threshold and will remain high until the fan
blades start rotating again.
On the ZXBM2002 variant this pin is Lock. During
normal operation the signal will be low and during a
Locked Rotor condition the pin will go high when the
C
LCK
pin reaches the V
THH
threshold.
For the ZXBM2003 variant this pin is FG. This signal is a
buffered and inverted output of the Hall signal and
therefore provides an output signal whose frequency
will be twice that of the rotational frequency of the fan.
7. C
LCK
- Locked Rotor timing capacitor
When in a Locked Rotor condition as described above
the Ph1 and Ph2 drive outputs go into a safe drive mode
to protect the external drive devices and the motor
windings. This condition consists of driving the motor
for a short period then waiting for a longer period
before trying again. The frequency at which this takes
place is determined by the size of the capacitor applied
to this CLCK pin. For a 12V supply a value of 1.0uF will
typically provide an ‘On’ (drive) period of 0.33s and an
‘Off’ (wait) period of 4.0s, giving an On:Off ratio of 1:12.
The C
LCK
timing periods are determined by the
following equations:
T
lock
=
V
THH
×
C
LCK
I
LCKC
(V
THH
−
V
THL
)
×
C
LCK
I
LCKD
(V
THH
−
V
THL
)
×
C
LCK
T
on
=
I
LCKC
T
off
=
This is the device supply ground return pin and will
generally be the most negative supply pin to the fan.
6. LOCK/FG
- Locked Rotor error output /
Frequency Generator (speed) output
This pin is an open collector output and so will require
an external pull up resistor for correct operation.
Where V
THH
and V
THL
are the C
LCK
pin threshold
voltages and I
LCKC
and I
LCKD
are the charge and
discharge currents.
ISSUE 4 - OCTOBER 2004
5
SEMICONDUCTORS
FPGA/CPLD
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