MC74VHC1G66
SPST (NO) Normally Open
Analog Switch
The MC74VHC1G66 is a single pole single throw (SPST) analog
switch. It achieves high speed propagation delays and low ON
resistances while maintaining low power dissipation. This bilateral
switch controls analog and digital voltages that may vary across the
full power−supply range (from V
CC
to GND).
The MC74VHC1G66 is compatible in function to a single gate of
the High Speed CMOS MC74VHC4066 and the metal−gate CMOS
MC14066. The device has been designed so that the ON resistances
(R
ON
) are much lower and more linear over input voltage than R
ON
of
the metal−gate CMOS or High Speed CMOS analog switches.
The ON/OFF control inputs are compatible with standard CMOS
outputs. The ON/OFF control input structure provides protection when
voltages between 0 V and 5.5 V are applied, regardless of the supply
voltage. This input structure helps prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup,
hot insertion, etc.
Features
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MARKING DIAGRAMS
5
SC−88A
DF SUFFIX
CASE 419A
V9 MG
G
M
1
5
1
TSOP−5
DT SUFFIX
CASE 483
1
V9 MG
G
5
•
•
•
•
•
•
•
•
High Speed: t
PD
= 20 ns (Typ) at V
CC
= 5.0 V
Low Power Dissipation: I
CC
= 1.0
mA
(Max) at T
A
= 25°C
Diode Protection Provided on Inputs and Outputs
Improved Linearity and Lower ON Resistance over Input Voltage
Chip Complexity: 11 FETs or 3 Equivalent Gates
ON/OFF Control Input has OVT
V9
= Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
Chip Complexity: FETs = 11
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PIN ASSIGNMENT
1
2
3
4
5
IN/OUT X
A
OUT/IN Y
A
GND
ON/OFF CONTROL
V
CC
FUNCTION TABLE
On/Off Control Input
L
H
State of Analog Switch
Off
On
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
©
Semiconductor Components Industries, LLC, 2015
1
September, 2016 − Rev. 17
Publication Order Number:
MC74VHC1G66/D
MC74VHC1G66
IN/OUT X
A
1
5
V
CC
IN/OUT X
A
1
6
V
CC
OUT/IN Y
A
2
OUT/IN Y
A
2
5
NC
GND
3
4
ON/OFF
CONTROL
GND
3
4
ON/OFF
CONTROL
(SC−88A, TSOP−5)
(UDFN6)
Figure 1. Pinout Diagrams
ON/OFF CONTROL
IN/OUT X
A
U
X1
1
1
U
OUT/IN
Y
A
Figure 2. Logic Symbol
MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
IS
I
IK
I
CC
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
DC Supply Voltage
Digital Input Voltage
Analog Output Voltage
Digital Input Diode Current
DC Supply Current, V
CC
and GND
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
Power Dissipation in Still Air at 85°C
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 28 to 34
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above V
CC
and Below GND at 125°C (Note 5)
SC70−5 (Note 1)
SOT23−5
SC70−5
SOT23−5
Characteristics
Value
−0.5 to +7.0
−0.5 to +7.0
−0.5 to V
CC
+0.5
−20
+25
*65
to
)150
260
)150
350
230
150
200
Level 1
UL 94 V−0 @ 0.125 in
u2000
u200
N/A
$500
V
Unit
V
V
V
mA
mA
°C
°C
°C
°C/W
mW
I
LATCHUP
Latchup Performance
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
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2
MC74VHC1G66
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
IS
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Operating Temperature Range
Input Rise and Fall Time
ON/OFF Control Input
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5.0 V
±
0.5 V
Characteristics
Min
2.0
GND
GND
−55
0
0
Max
5.5
5.5
V
CC
+125
100
20
Unit
V
V
V
°C
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
NORMALIZED FAILURE RATE
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature
°C
80
90
100
110
120
130
140
Time, Hours
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
Time, Years
117.8
47.9
20.4
9.4
4.2
2.0
1.0
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
T
J
=120
°
C
T
J
=100
°
C
T
J
= 90
°
C
T
J
= 80
°
C
100
T
J
= 130
°
C
T
J
=110
°
C
10
TIME, YEARS
1
1
1000
Figure 3. Failure Rate vs. Time Junction Temperature
DC ELECTRICAL CHARACTERISTICS
V
CC
(V)
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
0 to
5.5
5.5
3.0
4.5
5.5
5.5
T
A
= 25°C
Min
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
±0.1
Max
T
A
≤
85°C
Min
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
±1.0
Max
−55
≤
T
A
≤
125°C
Min
1.5
2.1
3.15
3.85
0.5
0.9
1.35
1.65
±1.0
Max
Unit
V
Symbol
V
IH
Parameter
Minimum High−Level
Input Voltage
ON/OFF Control Input
Maximum Low−Level
Input Voltage
ON/OFF Control Input
Maximum Input
Leakage Current
ON/OFF Control Input
Maximum Quiescent
Supply Current
Maximum ”ON”
Resistance
Maximum Off−Channel
Leakage Current
Test Conditions
R
ON
= Per Spec
V
IL
R
ON
= Per Spec
V
I
IN
V
IN
= V
CC
or GND
mA
I
CC
R
ON
V
IN
= V
CC
or GND
V
IO
= 0 V
V
IN
= V
IH
V
IS
= V
CC
or GND
|I
IS
|
≤
5 mA (Figure 4)
V
IN
= V
IL
V
IS
= V
CC
or GND
Switch Off (Figure 5)
1.0
60
45
40
0.1
20
70
50
45
0.5
40
100
60
55
1.0
mA
W
I
OFF
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
MC74VHC1G66
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AC ELECTRICAL CHARACTERISTICS
C
load
= 50 pF, Input t
r
/t
f
= 3.0 ns
V
CC
(V)
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
2.0
3.0
4.5
5.5
0.0
5.0
T
A
= 25°C
Typ
1
0.6
0.6
0.6
32
28
24
20
32
28
24
20
3
4
4
T
A
≤
85°C
−55
≤
T
A
≤
125°C
Min
Max
7
4
2
1
Symbol
t
PLH
,
t
PHL
Parameter
Test Conditions
Min
Max
5
2
1
1
Min
Max
6
3
1
1
Unit
ns
Maximum
Propagation Delay,
Input X to Y
Y
A
= Open
(Figure 14)
t
PLZ
,
t
PHZ
Maximum
Propagation Delay,
ON/OFF Control to Analog
Output
Maximum
Propagation Delay,
ON/OFF Control to
Analog Output
Maximum Input
Capacitance
R
L
= 1000
W
(Figure 15)
40
35
30
25
40
35
30
25
10
10
10
45
40
35
30
45
40
35
30
10
10
10
50
45
40
35
50
45
40
35
10
10
10
ns
t
PZL
,
t
PZH
R
L
= 1000
W
(Figure 15)
ns
C
IN
ON/OFF Control Input
Control Input = GND
Analog I/O
Feedthrough
pF
Typical @ 25°C, V
CC
= 5.0 V
18
C
PD
Power Dissipation Capacitance (Note 6)
pF
6. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
. C
PD
is used to determine the no−load dynamic
power consumption; P
D
= C
PD
V
CC2
f
in
+ I
CC
V
CC
.
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ADDITIONAL APPLICATION CHARACTERISTICS
(Voltages Referenced to GND Unless Noted)
Symbol
BW
Parameter
Test Conditions
V
CC
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Limit
25°C
150
175
180
Unit
Maximum On−Channel Bandwidth or
Minimum Frequency Response
(Figure 10)
Off−Channel Feedthrough Isolation
(Figure 11)
f
in
= 1 MHz Sine Wave
Adjust f
in
voltage to obtain 0 dBm at V
OS
Increase f
in
= frequency until dB meter reads −3 dB
R
L
= 50
W
f
in
= Sine Wave
Adjust f
in
voltage to obtain 0 dBm at V
IS
f
in
= 10 kHz, R
L
= 600
W
MHz
ISO
off
−80
−80
−80
dB
NOISE
feed
Feedthrough Noise Control to Switch
(Figure 12)
Total Harmonic Distortion
(Figure 13)
V
in
≤
1 MHz Square Wave (t
r
= t
f
= 2 ns)
R
L
= 600
W
45
60
130
mV
PP
THD
f
in
= 1 kHz, R
L
= 10 kW
THD = THD
Measured
− THD
Source
V
IS
= 3.0 V
PP
sine wave
V
IS
= 5.0 V
PP
sine wave
%
3.3
5.5
0.30
0.15
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MC74VHC1G66
PLOTTER
POWER
SUPPLY
-
+
V
CC
1
2
V
CC
3
4
A
3
4
5
V
CC
1
2
5
V
IL
V
CC
DC PARAMETER
ANALYZER
COMPUTER
Figure 4. On Resistance Test Set−Up
Figure 5. Maximum Off−Channel Leakage Current
Test Set−Up
V
CC
A
N/C
1
2
3
4
5
V
CC
1
V
IH
TEST
POINT
2
3
4
5
V
CC
V
CC
Figure 6. Maximum On−Channel Leakage Current
Test Set−Up
Figure 7. Propagation Delay Test Set−Up
Switch to Position 2 when testing t
PLZ
and t
PZL
Switch to Position 1 when testing t
PHZ
and t
PZH
TEST POINT
V
CC
1
1
2
V
CC
1
2
*Includes all probe and jig capacitance.
R
L
2
C
L
*
3
4
N/C
2
3
4
5
V
CC
N/C
1
5
V
CC
A
Figure 8. Propagation Delay Output Enable/Disable
Test Set−Up
Figure 9. Power Dissipation Capacitance
Test Set−Up
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