10AX032H2F35I2SG datasheet, PDF

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10AX032H2F35I2SG: DescriptionFPGA - Field Programmable Gate Array Arria 10 GX 320 FPGA; Categorysemiconductor Programmable logic devices; File Size384KB，42 Pages; ManufacturerAltera (Intel)

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10AX032H2F35I2SG Overview

FPGA - Field Programmable Gate Array Arria 10 GX 320 FPGA

10AX032H2F35I2SG Parametric

Parameter Name	Attribute value
Product Category	FPGA - Field Programmable Gate Array
Manufacturer	Altera (Intel)
RoHS	Details
Package / Case	FBGA-1152
Packaging	Tray
Moisture Sensitive	Yes
Factory Pack Quantity	24

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Intel

Arria

10 Device Overview

A10-OVERVIEW

2017.09.20

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Contents

Intel

Arria

10 Device Overview....................................................................................... 3

Key Advantages of Intel Arria 10 Devices........................................................................ 4

Summary of Intel Arria 10 Features................................................................................ 4

Intel Arria 10 Device Variants and Packages.....................................................................7

Intel Arria 10 GX.................................................................................................7

Intel Arria 10 GT............................................................................................... 11

Intel Arria 10 SX............................................................................................... 14

I/O Vertical Migration for Intel Arria 10 Devices.............................................................. 17

Adaptive Logic Module................................................................................................ 17

Variable-Precision DSP Block........................................................................................18

Embedded Memory Blocks........................................................................................... 20

Types of Embedded Memory............................................................................... 21

Embedded Memory Capacity in Intel Arria 10 Devices............................................ 21

Embedded Memory Configurations for Single-port Mode......................................... 22

Clock Networks and PLL Clock Sources.......................................................................... 22

Clock Networks................................................................................................. 22

Fractional Synthesis and I/O PLLs........................................................................22

FPGA General Purpose I/O........................................................................................... 23

External Memory Interface.......................................................................................... 24

Memory Standards Supported by Intel Arria 10 Devices......................................... 24

PCIe Gen1, Gen2, and Gen3 Hard IP............................................................................. 26

Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet............................................. 26

Interlaken Support............................................................................................ 26

10 Gbps Ethernet Support.................................................................................. 26

Low Power Serial Transceivers......................................................................................27

Transceiver Channels......................................................................................... 28

PMA Features................................................................................................... 29

PCS Features.................................................................................................... 30

SoC with Hard Processor System.................................................................................. 32

Key Advantages of 20-nm HPS............................................................................33

Features of the HPS...........................................................................................35

FPGA Configuration and HPS Booting................................................................... 37

Hardware and Software Development.................................................................. 37

Dynamic and Partial Reconfiguration............................................................................. 37

Dynamic Reconfiguration....................................................................................37

Partial Reconfiguration....................................................................................... 37

Enhanced Configuration and Configuration via Protocol.................................................... 38

SEU Error Detection and Correction.............................................................................. 39

Power Management.................................................................................................... 39

Incremental Compilation............................................................................................. 40

Document Revision History.......................................................................................... 40

Intel

Arria

10 Device Overview

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