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About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
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MB9A110A/MB9A110 Series
32-bit ARM
®
Cortex
®
-M3
FM3 Microcontroller
The MB9A110A/MB9A110 Series are highly integrated 32-bit microcontrollers that target for high-performance and cost-sensitive
embedded control applications.
The MB9A110A Series are based on the ARM
®
Cortex
®
-M3 Processor and on-chip Flash memory and SRAM, and peripheral
functions, including Motor Control Timers, ADCs, Communication Interfaces (UART, CSIO, I
2
C, LIN).
The products which are described in this datasheet are placed into TYPE1 product categories in “FM3 Family Peripheral Manual”.
Features
32-bit ARM
®
Cortex
®
-M3 Core
Processor version: r2p1
Up to 40 MHz Frequency Operation
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
[UART]
Full duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)*
24-bit System timer (Sys Tick): System timer for OS task
management
Various error detection functions available (parity errors,
On-chip Memories
[Flash memory]
Up to 512 Kbyte
Read cycle: 0 wait-cycle
Security function for code protection
[SRAM]
This Series contain a total of up to 32 Kbyte on-chip SRAM.
On-chip SRAM is composed of two independent SRAM
(SRAM0, SRAM1). SRAM0 is connected to I-code bus and
D-code bus of Cortex-M3 core. SRAM1 is connected to System
bus.
framing errors, and overrun errors)
*: MB9AF111LA, F112LA, F114LA, F112L and F114L do not
support Hardware Flow control
[CSIO]
Full duplex double buffer
Built-in dedicated baud rate generator
Overrun error detection function available
[LIN]
LIN protocol Rev.2.1 supported
Full duplex double buffer
Master/Slave mode supported
LIN break field generation (can be changed 13- 16bit length)
LIN break delimiter generation (can be changed 1 - 4bit
length)
SRAM0: Up to 16 Kbytes
SRAM1: Up to 16 Kbytes
Multi-function Serial Interface (Max 8 channels)
4 channels with 16 steps×9bit FIFO (ch.4-ch.7), 4 channels
without FIFO (ch.0-ch3)
Various error detection functions available (parity errors,
framing errors, and overrun errors)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
I
2
C
[I
2
C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps)
supported
Cypress Semiconductor Corporation
Document Number: 002-04672 Rev. *D
• 198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 12, 2017
MB9A110A/MB9A110 Series
External Bus Interface*
Supports SRAM, NOR Flash device
Up to 8 chip selects
8-/16-bit Data width
Up to 25-bit Address bit
Maximum area size: Up to 256 Mbytes
Supports Address/Data multiplex
Supports external RDY function
*: MB9AF111LA, F112LA and F114LA do not support
External Bus Interface
Multi-function Timer (Max 2 units)
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3 ch/unit
Input capture × 4 ch/unit
Output compare × 6 ch/unit
A/D activation compare × 3 ch/unit
Waveform generator × 3 ch/unit
16-bit PPG timer × 3 ch/unit
The following function can be used to achieve the motor
control.
DMA Controller (8 channels)
The DMA Controller has an independent bus from the CPU, so
CPU and DMA Controller can process simultaneously.
PWM signal output function
DC chopper waveform output function
Dead timer function
Input capture function
A/D converter activate function
DTIF (Motor emergency stop) interrupt function
Quadrature Position/Revolution Counter (QPRC)
(Max 2 units)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max 16 channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 3units*
Conversion time: 1.0 μs@5 V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16 steps, for Priority conversion: 4steps)
*: MB9AF111LA, F112LA, F114LA built-in 2units
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each timer
channel.
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from Low-Power
Consumption mode.
Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
Interval timer: up to 64 s(Max)@ Sub Clock: 32.768 kHz
Document Number: 002-04672 Rev. *D
Page 2 of 111
MB9A110A/MB9A110 Series
Watch dog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
The "Hardware" watchdog timer is clocked by the built-in
low-speed CR oscillator. Therefore, the "Hardware" watchdog
is active in any low-power consumption modes except STOP
modes.
[Resets]
Reset requests from INITX pin
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detector reset
Clock Supervisor reset
Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to
supervise abnormality of the external clocks.
External Interrupt Controller Unit
Up to 16 external interrupt input pins
Include one non-maskable interrupt (NMI) input pin
General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set which I/O port the
peripheral function can be allocated to.
External clock failure (clock stop) is detected, reset is
asserted.
External frequency anomaly is detected, interrupt or reset is
asserted.
Low-Voltage Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC.
When the voltage falls below the voltage that has been set,
Low-Voltage Detector generates an interrupt or reset.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 83 fast General Purpose I/O Ports@ 100 pin Package
Some ports are 5V tolerant I/O (MB9AF115MA/NA,
MB9AF116MA/NA only)
Please see "Pin Description" to confirm the corresponding
pins.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Three Low-Power Consumption modes supported.
SLEEP
TIMER
STOP
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM)*
*: Mb9AF111LA/MA, F112LA/MA, F114LA/MA, F115MA and
F116MA support only SWJ-DP.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy
software processing load, and achieves a reduction of the
integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2
built-in CR oscillators, and Main PLL).
Power Supply
VCC = 2.7 V to 5.5 V: Correspond to the wide range voltage.
Main Clock:
Sub Clock:
Built-in High-speed CR Clock:
Built-in Low-speed CR Clock:
Main PLL Clock
4 MHz to 48 MHz
32.768 kHz
4 MHz
100 kHz
Document Number: 002-04672 Rev. *D
Page 3 of 111
MB9A110A/MB9A110 Series
Contents
1. Product Lineup .................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment ................................................................................................................................................................. 8
4. List of Pin Functions....................................................................................................................................................... 14
5. I/O Circuit Type................................................................................................................................................................ 39
6. Handling Precautions ..................................................................................................................................................... 44
6.1
Precautions for Product Design ................................................................................................................................... 44
6.2
Precautions for Package Mounting .............................................................................................................................. 45
6.3
Precautions for Use Environment ................................................................................................................................ 46
7. Handling Devices ............................................................................................................................................................ 47
8. Block Diagram ................................................................................................................................................................. 49
9. Memory Size .................................................................................................................................................................... 50
10. Memory Map .................................................................................................................................................................... 50
11. Pin Status in Each CPU State ........................................................................................................................................ 54
12. Electrical Characteristics ............................................................................................................................................... 58
12.1 Absolute Maximum Ratings ......................................................................................................................................... 58
12.2 Recommended Operating Conditions.......................................................................................................................... 60
12.3 DC Characteristics....................................................................................................................................................... 61
12.3.1 Current rating ............................................................................................................................................................... 61
12.3.2 Pin Characteristics ....................................................................................................................................................... 63
12.4 AC Characteristics ....................................................................................................................................................... 64
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 64
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 65
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 65
12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input clock of PLL) ......................................... 66
12.4.5 Operating Conditions of Main PLL (In the case of using the built-in high speed CR for the input clock
of the main PLL) ........................................................................................................................................................... 66
12.4.6 Reset Input Characteristics .......................................................................................................................................... 67
12.4.7 Power-on Reset Timing................................................................................................................................................ 67
12.4.8 External Bus Timing ..................................................................................................................................................... 68
12.4.9 Base Timer Input Timing .............................................................................................................................................. 75
12.4.10 CSIO/UART Timing .................................................................................................................................................. 76
12.4.11 External Input Timing ................................................................................................................................................ 84
12.4.12 Quadrature Position/Revolution Counter timing ........................................................................................................ 85
12.4.13 I
2
C Timing ................................................................................................................................................................. 87
12.4.14 ETM timing ............................................................................................................................................................... 88
12.4.15 JTAG Timing ............................................................................................................................................................. 89
12.5 12-bit A/D Converter .................................................................................................................................................... 90
12.6 Low-voltage detection characteristics .......................................................................................................................... 93
12.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 94
12.7.1 Write / Erase time......................................................................................................................................................... 94
12.7.2 Erase/Write cycles and data hold time ......................................................................................................................... 94
12.8 Return Time from Low-Power Consumption Mode ...................................................................................................... 95
12.8.1 Return Factor: Interrupt ................................................................................................................................................ 95
12.8.2 Return Factor: Reset .................................................................................................................................................... 97
13. Ordering Information ...................................................................................................................................................... 99
14. Package Dimensions .................................................................................................................................................... 100
15. Errata.............................................................................................................................................................................. 107
Document Number: 002-04672 Rev. *D
Page 4 of 111
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