Changes to Ordering Guide .......................................................... 41
12/13—Revision 0: Initial Version
Rev. C | Page 2 of 42
Data Sheet
SPECIFICATIONS
AD7091R-2/AD7091R-4/AD7091R-8
V
DD
= 2.7 V to 5.25 V, V
DRIVE
= 1.8 V to 5.25 V, V
REF
= 2.5 V internal reference, f
SAMPLE
= 1 MSPS, f
SCLK
= 50 MHz, T
A
= T
MIN
to T
MAX
, unless
otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Signal-to-Noise-and-Distortion (SINAD) Ratio
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Channel-to-Channel Isolation
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Offset Error Matching
Offset Error Drift
Gain Error
Gain Error Matching
Gain Error Drift
ANALOG INPUT
Input Voltage Range
1
DC Leakage Current
Input Capacitance
2
Multiplexer On Resistance
VOLTAGE REFERENCE INPUT/OUTPUT
REF
OUT 3
REF
IN3
Drift
Power-On Time
LOGIC INPUTS
Input High Voltage (V
IH
)
Input Low Voltage (V
IL
)
Input Current (I
IN
)
LOGIC OUTPUTS
Output High Voltage (V
OH
)
Output Low Voltage (V
OL
)
Floating State Leakage Current
Output Coding
Test Conditions/Comments
f
IN
= 10 kHz sine wave
Min
66.5
65.5
f
IN
= 1 kHz sine wave
Typ
70
69
−80
−81
−95
5
40
1.5
1.2
Max
Unit
dB
dB
dB
dB
dB
ns
ps
MHz
MHz
Bits
LSB
LSB
LSB
mV
mV
ppm/°C
% FS
% FS
ppm/°C
V
µA
pF
pF
Ω
Ω
V
V
ppm/°C
ms
V
V
µA
V
V
µA
At −3 dB
At −0.1 dB
12
−1
−1.25
−0.9
−1.5
−1.5
−0.1
−0.1
V
DD
≥ 3.0 V
V
DD
≥ 2.7 V
Guaranteed no missing codes to 12 bits
T
A
= 25°C
T
A
= 25°C
T
A
= 25°C
T
A
= 25°C
±0.7
±0.8
±0.3
0.2
0.2
2
0.0
0.0
2
+1
+1.25
+0.9
+1.5
+1.5
+0.1
+0.1
At ADC
IN
During acquisition phase
Outside acquisition phase
V
DD
= 5.0 V
V
DD
= 2.5 V
Internal reference output, T
A
= 25°C
External reference input
C
REF
= 2.2 µF
0
−1
10
1.5
50
100
2.49
1.0
2.5
5
50
0.7 × V
DRIVE
V
REF
+1
2.51
V
DD
Typically 10 nA, V
IN
= 0 V or V
DRIVE
I
SOURCE
= 200 µA
I
SINK
= 200 µA
−1
V
DRIVE
− 0.2
−1
0.3 × V
DRIVE
+1
0.4
+1
Straight (natural) binary
Rev. C | Page 3 of 42
AD7091R-2/AD7091R-4/AD7091R-8
Parameter
CONVERSION RATE
Conversion Time
Transient Response
Throughput Rate
POWER REQUIREMENTS
V
DD
V
DRIVE
V
DRIVE
Range
4
I
DD
Normal Mode—Static
5
Normal Mode—Operational
Power-Down Mode
Test Conditions/Comments
Min
Typ
Max
600
400
1
2.7
2.7
1.8
22
21.6
500
450
0.550
0.550
0.435
2
1
30
10
5.25
5.25
5.25
50
46
570
530
17
6
15
4
3.5
70
15
1
1
0.290
0.149
3.4
1.7
95
33
50
Data Sheet
Unit
ns
ns
MSPS
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mW
mW
mW
mW
mW
µW
µW
µW
Full-scale step input
I
DRIVE
Normal Mode—Static
6
Normal Mode—Operational
Power-Down Mode
Total Power Dissipation
7
Normal Mode—Static
Normal Mode—Operational
Power-Down Mode
Specified performance
Functional
V
IN
= 0 V
V
DD
= 5.25 V
V
DD
= 3 V
V
DD
= 5.25 V, f
SAMPLE
= 1 MSPS
V
DD
= 3 V, f
SAMPLE
= 1 MSPS
V
DD
= 5.25 V
V
DD
= 5.25 V, T
A
= −40°C to +85°C
V
DD
= 3 V
V
IN
= 0 V
V
DRIVE
= 5.25 V
V
DRIVE
= 3 V
V
DRIVE
= 5.25 V, f
SAMPLE
= 1 MSPS
V
DRIVE
= 3 V, f
SAMPLE
= 1 MSPS
V
DRIVE
= 5.25 V
V
DRIVE
= 3 V
V
IN
= 0 V
V
DD
= V
DRIVE
= 5.25 V
V
DD
= V
DRIVE
= 3 V
V
DD
= V
DRIVE
= 5.25 V, f
SAMPLE
= 1 MSPS
V
DD
= V
DRIVE
= 3 V, f
SAMPLE
= 1 MSPS
V
DD
= V
DRIVE
= 3 V, f
SAMPLE
= 100 SPS
V
DD
= 5.25 V
V
DD
= 5.25 V, T
A
= −40°C to +85°C
V
DD
= V
DRIVE
= 3 V
0.130
0.070
2.8
1.4
0.080
3
3
1.4
Multiplexer input voltage should not exceed V
DD
.
Sample tested during initial release to ensure compliance.
3
When referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configurations and Function Descriptions section.
4
Device is functional and meets dynamic performance/dc accuracy specifications with V
DRIVE
down to 1.8 V, but the device is not capable of achieving a throughput of
1 MSPS.
5
SCLK operates in burst mode, and CS idles high. With a free running SCLK and CS pulled low, the I
DD
static current is increased by 30 µA typical at V
DD
= 5.25 V.
6
SCLK operates in burst mode, and CS idles high. With a free running SCLK and CS pulled low, the I
DRIVE
static current is increased by 32 µA typical at V
DRIVE
= 5.25 V.
7
Total power dissipation includes contributions from V
DD
, V
DRIVE
, and REF
IN
(see Note 2).
1
2
Rev. C | Page 4 of 42
Data Sheet
TIMING SPECIFICATIONS
AD7091R-2/AD7091R-4/AD7091R-8
V
DD
= 2.7 V to 5.25 V, V
DRIVE
= 1.8 V to 5.25 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
Conversion Time: CONVST Falling Edge to Data Available
Acquisition Time
Time Between Conversions (Normal Mode)
CONVST Pulse Width
SCLK Period (Normal Mode)
V
DRIVE
Above 2.7 V
V
DRIVE
Above 1.8 V
SCLK Period (Chain Mode)
V
DRIVE
Above 2.7 V
V
DRIVE
Above 1.8 V
SCLK Low Time
SCLK High Time
SCLK Falling Edge to Data Remains Valid
SCLK Falling Edge to Data Valid Delay
V
DRIVE
Above 4.5 V
V
DRIVE
Above 3.3 V
V
DRIVE
Above 2.7 V
V
DRIVE
Above 1.8 V
End of Conversion to CS Falling Edge
CS Low to SDO Enabled
CS High or Last SCLK Falling Edge to SDO High Impedance
SDI Data Setup Time Prior to SCLK Rising Edge
SDI Data Hold Time After SCLK Rising Edge
Last SCLK Falling Edge to Next CONVST Falling Edge
RESET Pulse Width
RESET Pulse Delay Upon Power Up
Time Between Conversions (Power On Software Reset)
Symbol
t
CONVERT
t
ACQ
t
CYC
t
CNVPW
t
SCLK
Min
400
1000
10
16
22
t
SCLK
20
25
6
6
5
12
13
14
20
t
EOCCSL
t
EN
t
DIS
t
SSDISCLK
t
HSDISCLK
t
QUIET
t
RESETPW
t
RESET_DELAY
t
CYC_RESET
5
5
5
5
2
50
10
50
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
Typ
Max
600
Unit
ns
ns
ns
ns
ns
ns
500
t
SCLKL
t
SCLKH
t
HSDO
t
DSDO
500µA
I
OL
X% V
DRIVE
Y% V
DRIVE
t
DELAY
TO SDO
C
L
20pF
10891-138
t
DELAY
V
IH2
V
IL2
V
IH2
V
IL2
10891-139
1.4V
500µA
I
OH
NOTES
1FOR
V
DRIVE
≤
3.0V, X = 90 AND Y = 10; FOR
V
DRIVE
> 3.0V, X = 70 AND Y = 30.
2MINIMUM VIH AND MAXIMUM VIL USED. SEE SPECIFICATIONS FOR DIGITAL
INPUTS PARAMETER IN TABLE 2.
Figure 2. Load Circuit for Digital Interface Timing
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