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ICS950812CGLF

Description
Clock Generators u0026 Support Products
Categorysemiconductor    Analog mixed-signal IC   
File Size1008KB,30 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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ICS950812CGLF Overview

Clock Generators u0026 Support Products

ICS950812CGLF Parametric

Parameter NameAttribute value
Product CategoryClock Generators & Support Products
ManufacturerIDT (Integrated Device Technology, Inc.)
DATASHEET
Frequency Generator with 200MHz Differential
CPU Clocks
Recommended Application:
CK-408 clock with Buffered/Unbuffered mode supporting
Almador, Brookdale, ODEM, and Montara-G chipsets with PIII/
P4 processor. Programmable for group to group skew.
Output Features:
3 0.7V Differential CPU Clock Pairs
7 PCI (3.3V) @ 33.3MHz including 2 early PCI clocks
3 PCI_F (3.3V) @ 33.3MHz
1 USB (3.3V) @ 48MHz, 1 DOT (3.3V) @ 48MHz
1 REF (3.3V) @ 14.318MHz
5 3V66 (3.3V) @ 66.6MHz
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
Provides standard frequencies and additional 5%
and 10% over-clocked frequencies
Supports spread spectrum modulation:
No spread, Center Spread (±0.35%, ±0.5%,
or ±0.75%), or Down Spread (-0.5%, -1.0%, or -1.5%)
Offers adjustable PCI early clock via latch inputs
Selectable 1X or 2X strength for REF via I
2
C interface
Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Uses external 14.318MHz crystal
Stop clocks and functional control available through I
2
C
interface.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
66MHz Output Jitter (Additive) (Buffered Mode) <100ps
CPU Output Skew <100ps
Pin Configuration
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
**E_PCICLK1/PCICLK1
PCICLK2
**E_PCICLK3/PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
66MHZ_OUT0/3V66_2
66MHZ_OUT1/3V66_3
66MHZ_OUT2/3V66_4
66MHZ_IN/3V66_5
*PD#
VDDA
GND
Vtt_PWRGD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
ICS950812
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF
FS1
FS0
CPU_STOP#*
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTSEL*
IREF
GND
FS2
48MHz_USB/FS3
**
48MHz_DOT
VDD48
GND
3V66_1/VCH_CLK/FS4
**
PCI_STOP#*
3V66_0/FS5
**
VDD3V66
GND
SCLK
SDATA
56-Pin 300mil SSOP
6.10 mm. Body, 0.50 mm. pitch TSSOP
*
**
These inputs have 120K internal pull-up resistors to VDD.
Internal pull-down resistors to ground.
Note:
Almador board level designs MUST use pin 22,
66MHZ_OUT1, as the feedback connection from the clock
buffer path to the Almador (GMCH) chipset.
Block Diagram
PLL2
48MHz_USB
48MHz_DOT
Frequency Select
Bit
CPUCLK
MHz
66.66
100.00
200.00
133.33
66.66
100.00
200.00
133.33
3V66
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66MHz_OU
T (2:0)
3V66 (4:2)
MHz
66.66
66.66
66.66
66.66
66MHz_IN
66MHz_IN
66MHz_IN
66MHz_IN
66MHz_IN
3V66_5
MHz
66.66
66.66
66.66
66.66
Input
Input
Input
Input
PCICLK_F
PCICLK
MHz
33.33
33.33
33.33
33.33
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
66MHz_IN/2
X1
X2
XTAL
OSC
3V66_5/66MHz_IN
3V66_3/66MHz_OUT1
3V66_(4,2)/66MHz_OUT(2,0)
PLL1
Spread
Spectrum
PD#
CPU_STOP#
PCI_STOP#
MULTSEL
FS (5:0)
SDATA
SCLK
V
TT
_PWRGD#
REF
CPU
DIVDER
Stop
3
3
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK (6:4, 2, 0)
PCI
DIVDER
Stop
5
Control
Logic
3V66
DIVDER
E_PCICLK(1,3)/PCICLK(1,3)
2
3
PCICLK_F
(2:0)
3V66_0
Config.
Reg.
3V66_1/VCH_CLK
I REF
FS2 FS1 FS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
IDT
TM
Frequency Generator with 200MHz Differential CPU Clocks
ICS950812
0542K—03/23/16
1

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