FemtoClock
®
NG Octal Universal
Frequency Translator
8T49N287
Datasheet
Description
The 8T49N287 has two independent, fractional-feedback PLLs that
can be used as jitter attenuators and frequency translators. It is
equipped with six integer and two fractional output dividers, allowing
the generation of up to 8 different output frequencies, ranging from
8kHz to 1GHz. Four of these frequencies are completely independent
of each other and the inputs. The other four are related frequencies.
The eight outputs may select among LVPECL, LVDS, HCSL, or
LVCMOS output levels.
This makes it ideal to be used in any frequency translation
application, including 1G, 10G, 40G and 100G Synchronous Ethernet,
OTN, and SONET/SDH, including ITU-T G.709 (2009) FEC rates.
The device may also behave as a frequency synthesizer.
The 8T49N287 accepts up to two differential or single-ended input
clocks and a crystal input. Each of the two internal PLLs can lock to
different input clocks which may be of independent frequencies. Each
PLL can use the other input for redundant backup of the primary
clock, but in this case, both input clocks must be related in frequency.
The device supports hitless reference switching between input clocks.
The device monitors all input clocks for Loss of Signal (LOS), and
generates an alarm when an input clock failure is detected. Automatic
and manual hitless reference switching options are supported. LOS
behavior can be set to support gapped or un-gapped clocks.
The 8T49N287 supports holdover for each PLL. The holdover has an
initial accuracy of ±50ppB from the point where the loss of all
applicable input reference(s) has been detected. It maintains a
historical average operating point for each PLL that may be returned
to in holdover at a limited phase slope.
The device places no constraints on input to output frequency conver-
sion, supporting all FEC rates, including the new revision of ITU-T Rec-
ommendation G.709 (2009), most with 0ppm conversion error.
Each PLL has a register-selectable loop bandwidth from 1.4Hz to
360Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I
2
C interface. It also supports
I
2
C master capability to allow the register configuration to be read
from an external EEPROM.
Features
•
•
•
•
•
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
<0.3ps RMS Typical jitter (including spurs), 12kHz to 20MHz
Operating modes: locked to input signal, holdover and free-run
Initial holdover accuracy of ±50ppb
Accepts up to two LVPECL, LVDS, LVHSTL, HCSL, or LVCMOS
input clocks
•
•
•
•
•
•
•
Accepts frequencies ranging from 8kHz up to 875MHz
Auto and manual input clock selection with hitless switching
Clock input monitoring, including support for gapped clocks
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
Operates from a 10MHz to 40MHz fundamental-mode crystal
Generates 8 LVPECL / LVDS / HCSL or 16 LVCMOS output clocks
•
•
•
•
•
•
•
•
•
•
Output frequencies ranging from 8kHz up to 1.0GHz (diff)
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
Four General Purpose I/O pins with optional support for status &
control:
Four Output Enable control inputs may be mapped to any of the
eight outputs
Lock, Holdover and Loss-of-Signal status outputs
Open-drain Interrupt pin
Nine programmable loop bandwidth settings for each PLL from
1.4Hz to 360Hz
•
Optional Fast Lock function
Programmable output phase delays in steps as small as 16ps
Register programmable through I
2
C or via external I
2
C EEPROM
Bypass clock paths for system tests
Power supply modes
V
CC
/ V
CCA
/ V
CCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
-40°C to 85°C ambient operating temperature
Package: 56QFN, lead-free (RoHS 6)
Typical Applications
•
•
•
•
•
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•
OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
OTN de-mapping (Gapped Clock and DCO mode)
Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
SyncE (G.8262) applications
Wireless base station baseband
Data communications
100G Ethernet
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•
©2018 Integrated Device Technology, Inc.
1
January 31, 2018
8T49N287 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
3
4
5
12
13
7
8
9
10
48, 47
44, 43
27, 28
23, 24
40, 39
37, 36
34, 33
31, 30
46
Name
OSCI
OSCO
S_A0
SDATA
SCLK
CLK0
nCLK0
CLK1
nCLK1
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
nRST
I
O
I
I/O
I/O
I
I
I
I
O
O
O
O
O
O
O
O
I
Pulldown
Pullup
Pullup
Pulldown
Pullup /
Pulldown
Pulldown
Pullup /
Pulldown
Universal
Universal
Universal
Universal
Universal
Universal
Universal
Universal
Pullup
Type
Description
Crystal Input. Accepts a 10MHz-40MHz reference from a clock oscillator or a
12pF fundamental mode, parallel-resonant crystal.
Crystal Output. This pin should be connected to a crystal. If an oscillator is
connected to OSCI, then this pin must be left unconnected.
I
2
C lower address bit A0.
I
2
C interface bi-directional Data.
I
2
C interface bi-directional Clock.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 when left floating (set by the internal
pullup and pulldown resistors.)
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 when left floating (set by the internal
pullup and pulldown resistors.)
Output Clock 0. Please refer to the
Output Drivers
section for more details.
Output Clock 1. Please refer to the
Output Drivers
section for more details.
Output Clock 2. Please refer to the
Output Drivers
section for more details.
Output Clock 3. Please refer to the
Output Drivers
section for more details.
Output Clock 4. Please refer to the
Output Drivers
section for more details.
Output Clock 5. Please refer to the
Output Drivers
section for more details.
Output Clock 6. Please refer to the
Output Drivers
section for more details.
Output Clock 7. Please refer to the
Output Drivers
section for more details.
Master Reset input. LVTTL / LVCMOS interface levels:
0 = All registers and state machines are reset to their default values
1 = Device runs normally
50
29, 42, 21, 25
54
6, ePad
11
17
2
14, 15, 16, 20
1, 51, 55, 56
49
45
26
22
nINT
GPIO[3:0]
PLL_BYP
V
EE
V
CC
V
CC
V
CCA
V
CCA
V
CCA
V
CCO0
V
CCO1
V
CCO2
V
CCO3
O
I/O
I
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Open-drain
with pullup Interrupt output.
Pullup
Pulldown
General-purpose input-outputs. LVTTL / LVCMOS Input levels Open-drain
output. Pulled-up with 5.1k resistor to V
CC.
Bypass Selection. Allow input references to bypass both PLLs.
LVTTL / LVCMOS interface levels.
Negative supply voltage. All V
EE
pins and EPAD must be connected before any
positive supply voltage is applied.
Core and digital functions supply voltage.
Core and digital functions supply voltage.
Analog functions supply voltage for core analog functions.
Analog functions supply voltage for analog functions associated with PLL1.
Analog functions supply voltage for analog functions associated with PLL0.
High-speed output supply voltage for output pair Q0, nQ0.
High-speed output supply voltage for output pair Q1, nQ1.
High-speed output supply voltage for output pair Q2, nQ2.
High-speed output supply voltage for output pair Q3, nQ3.
©2018 Integrated Device Technology, Inc.
4
January 31, 2018
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