PLUTO
Dual Mode CDMA/AMPS Baseband Interface
Advance Information
DS4722 - 1.8 July 1998
The PLUTO baseband interface circuit is designed for use
in dual mode CDMA/AMPS digital cellular telephones. In the
telephone, Pluto provides the interface between the radio (RF
& IF) components and the baseband digital signal processor.
Pluto is part of a complete chipset solution for CDMA phones
entitled the Planet chipset.
The receive (RX) section converts the analog in-phase and
quadrature (I & Q) signals into equivalent digital signals whilst
the transmit (TX) circuits perform the complementary function
of translating digital baseband information into the analog
equivalent signals required for the modulator in the radio
circuits. VHF PLLS are also included for second RXLO and
TXIF generation.
PLUTO also contains a 4 channel general purpose ADC
which is included for such purposes as environmental and
signal strength monitoring.
PIN 1 IDENT
PIN 80
FEATURES
s
Dual mode AMPS/CDMA compatible
s
Low Power/Low Voltage operation
s
Standard baseband I and Q interface
s
4 Input Auxiliary ADC
s
Synthesisers
APPLICATIONS
s
Dual Mode CDMA/AMPs digital cellular
telephones
TXQ,TXQ-
FM_MOD
TXIF PD_RX
PD_TX
RXIF
TXI,TXI-
PIN 1
GP80
MP28
Figure 1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Voltage applied to any other pin
Operating junction temperature
Storage temperature
ESD (human body model)
ORDERING INFORMATION
PLUTO/KG/GP1R
ADC<3> ADC<1>
FC_I
I+,I-
BAL
Q+,Q-
FC_Q
ADC<2> ADC<0>
-0.3 to 3.9V
-0.3 to Vcc+0.3V
150°C
-55°C to 150°C
2kV
TX
SYNTH
TCXO/4
/4
RX
SYNTH
8-BIT
DAC
8-BIT
DAC
8-BIT
DAC
ANALOG
MULTIPLEXER
S<0>
S<1>
VDD
GND
1025
CHIPx8
512
8-BIT
DAC
8-BIT
DAC
8-BIT 6-BIT
ADC ADC
6-BIT 8-BIT
ADC ADC
8-BIT
ADC
SUB
FM/
SLEEP/
IDLE/
RESET/
19.68MHz
BUFFER
tx calibration and control
rx calibration and control
SDATA
SCLOCK
TCXO
TXCLK
TXD<7:0>
RXIFMDATA
RXID<3:0>
ADCENA
ADCDATA
ADCCLK
RXQFMDATA
RXQD<3:0>
SLATCH
Figure 2 Block diagram
PLUTO
PIN DESCRIPTION
No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Pin Name
VDD
RSET
GND
TX_IF
IDLEB
PD TX
FMB
PD_RX
SLEEPB
RX_IF
TX_LOCK
RX_LOCK
TCXO/4
TXD<0>
TXD<1>
TXD<2>
TXD<3>
TXD<4>
TXD<5>
TXD<6>
TXD<7>
TXCLK
TXCLKB
CHIPx8
VDD
TCXO
GND
SUB
RESET
SDATA
SCLK
SLATCH
S<0>
n/c
RXID<0>
RXID<1>
RXID<2>
RXID<3>
S<1>
n/c
RXQD<0>
RXQD<1>
RXQD<2>
RXQD<3>
GND
VDD
RXFMSTB
FMCLK
RXQFMDATA
RXIFMDATA
ADCLK
ADCDATA
ADCENA
SUB
Type
Power
Input
Ground
Input
Digital
Output
Input
Output
Input
Input
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power
Input
Ground
Ground
Input
Input
Input
Input
Input
Output
Output
Output
Output
Input
Output
Output
Output
Output
Ground
Power
input
Input
Output
Output
Output
Output
Input
Ground
A/D
Analog
Analog
Description
Power Supply
Bias current setting resistor - 40kΩ to ground
Ground
TX VCO output
Idle mode control signal - active low - pulled low if left unconnected
TX synthesiser charge pump output
FM mode control signal - active low - pulled low if left unconnected
RX synthesiser charge pump output
Sleep mode control signal - active low - pulled low if left unconnected
RX VCO output
TX synthesiser lock detect open drain output - pulled high by ext. resistor
RX synthesiser lock detect open drain output - pulled high by ext. resistor
TCXO divided by 4 output
Transmit data bit 0 (lsb)
Transmit data bit 1
Transmit data bit 2
Transmit data bit 3
Transmit data bit 4
Transmit data bit 5
Transmit data bit 6
Transmit data bit 7 (MSB)
Complimentary Transmit Clock (+ve)
Complementary Transmit Clock (-ve)
9.8304MHz synthesiser output
Power Supply
TCXO 19.68MHz a.c. coupled sinewave input
Ground
Substrate-Ground
Chip master reset - pulled high if not connected
Serial Interface Data Input
Serial Interface Clock Input
Serial Interfce Latch Input
Aux ADC mux channel select LSB
I-Channel RX CDMA output LSB - low when inactive
I-Channel RX CDMA output bit 1 - low when inactive
I-Channel RX CDMA output bit 2 - low when inactive
I-Channel RX CDMA output bit 3 - low when inactive
Aux ADC mux channel select MSB
Q_Channel RX CDMA output LSB - low when inactive
Q_Channel RX CDMA output bit 1 - low when inactive
Q_Channel RX CDMA output bit 2 - low when inactive
Q_Channel RX CDMA output bit 3 - low when inactive
Ground
Power Supply
Receive data FM strobe - pulled low if not connected
Receive data FM clock - pulled low if not connected
Q-Channel RX FM data serial output - low when inactive
I-Channel RX FM data serial output -low when inactive
Auxiliary ADC serial data clock. Low when inactive
Auxiliary ADC serial data output. Low when inactive
Auxiliary ADC enable - pull down if not used
Substrate - Ground
Digital
Analog
Digital
Analog
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Analog
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
2
PLUTO
PIN DESCRIPTION (continued)
No
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin Name
RXQP
RXQM
SUB
RXIP
RXIM
VDD
GND
VREF<0>
AD<0>
AD<1>
AD<2>
AD<3>
Vtest
EnTest
FC_Q
FC_I
BAL
VDD
GND
TXIP
TXIM
SUB
TXQP
TXQM
FMTX
VREF<1>
Type
Input
Input
Ground
Input
Input
Power
Ground
Input/Output
Input
Input
Input
Input
Output
Output
Output
Output
Output
Power
Ground
Output
Output
Ground
Output
Output
Output
Input/Output
A/D
Analog
Analog
Analog
Analog
Description
Receive Q Channel Input (+ve)
Receive Q Channel Input (-ve)
Substrate - Ground
Receive Q channel input (+ve)
Receive Q channel Input (-ve)
Power Supply
Ground
CDMA Receive Circuit Voltage Reference De-Coupling
AUX ADC Input
AUX ADC Input
AUX ADC Input
AUX ADC Input
RX Filter tuning tone output - pulled low when inactive
RX Filter tuning mode control output - pulled low when inactive
RX Filter Q channel FC control
RX Filter channel FC control
RX Filter Gain Balance Control
Power Supply
Ground
Transmit Circuit channel Complementary Output (+ve)
Transmit Circuit I channel Complementary Output (-ve)
Substrate - Ground
Transmit Circuit Q channel Complementary Output (+ve)
Transmit Circuit Q channel Complementary Output (-ve)
Transmit Circuit FM output
Transmit Circuit Voltage Reference De-coupling
Analog
Analog
Analog
Analog
Analog
Digital
Digital
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
FUNCTIONAL DESCRIPTION
Baseband TX interface circuit
The Pluto baseband transmit circuit acts as an interface
between the baseband signal processor and the RF/IF sections
in a CDMA/AMPS compatible mobile telephone.
The TX circuit has two modes of operation :
CDMA mode, transmit data that has previously been encoded
by the baseband digital signal processor is converted to
equivalent analog signals by matched digital-to-analog
converters, these signals are then filtered to remove the image
of the sample clock that would otherwise be present at the
output before being output to the I and Q modulator as
differential signals.
FM mode, transmit data is treated in much the same way as
in CDMA mode except that only one DAC is used and (because
of the much lower bandwidth of AMPS signals) a different
reconstruction filter is used before the analog fm signal is output
to the mixer as a single ended signal.
CDMA Transmit Signal Path
CDMA TX DACs
In CDMA mode two matched 8-bit DACs are used to
generate the in-phase and quadrature signals, the input
data for the DACs is obtained by multiplexing over an 8-bit
parallel input port (TXD<7:0>). The transmit data rate is
twice as fast as the differential transmit clock (TXCLK).
Incoming data that is valid during the rising edge of the
transmit clock is loaded into in In-Phase DAC & incoming
data that is valid on the falling edge of the transmit clock is
loaded into the Quadrature DAC - I and Q values must be
modified in the digital baseband chip to account for the half-
cycle delay between them.
CDMA Analog Reconstruction Filters
The frequency spectrum at the output of the transmit
DACs contains unwanted frequency components.
Reconstruction filters are used to smooth the DAC output
signals, providing continuous time output signals at the I and
Q output pins thereby removing these undesirable signals.
The low pass filters used are 5th order Butterworth,
continuous time filters with a nominal cut-off frequency of 1.2
MHz. These filters are designed to have a linear phase
response in the pass band. On-chip reconstruction filters
minimise the phase and amplitude mismatch between I and
Q channels.
3
PLUTO
CDMA TX Section Analog Interface
The ITx and QTx outputs can be d.c. or a.c. coupled to the
external circuits and will differentially drive a minimum
resistive load of 5 kΩ and a maximum capacitive load of 20 pF.
When the CDMA transmit path is in power-down mode the
positive outputs goes high and the negative output goes low.
FM Transmit Signal Path
FM TX DAC
In FM mode, the Q-Channel DAC is used to generate an
analog FM modulation signal from the data transmitted from
the digital baseband processor. In this mode, all other CDMA
TX circuits are powered down.
FM Mode Analog Reconstruction Filters
The frequency spectrum at the output of the transmit DAC
contains unwanted frequency components. A reconstruction
filter is used to smooth the DAC output signals.
Low-pass filters are used with a cut-off frequency of
approximately 13 kHz. These filters are 3rd order Butterworth
filters.
FM TX Section Analog Interface
The FMTX output can be d.c. or a.c. coupled to the radio
circuits and will drive a minimum resistive load of 5 kΩ and a
maximum capacitive load of 20 pF.
When the FM mode is in power-down the output is in high
impedance state.
CDMA Receive Signal Path
CDMA Receive ADC
In CDMA mode two high speed 4-bit ADCs are used to
digitise the incoming signals before subsequent transmission
to the baseband digital signal processor as two parallel 4 bit
words (RXI<3:0> and RXQ<3:0>). The sample rate of
9.8304MHz is generated via an on chip synthesiser that
requires no setting up or external components. On each falling
edge of the synthesised clock (CHIPx8) a new digital sample
is output on the digital bus.
CDMA Receive Calibration Circuit
On entering into CDMA mode from power down or from FM
mode the calibration circuits are activated. These circuits
measure the differences between the receive path gain in the
pass band and in the transition band of both I and Q filters. Via
a successive approximation process they tune the receive
filters cut-off frequency and amplitude matching using the 8 bit
DACs provided for this purpose (I_FC, Q_FC and BAL). Once
both filters (I and Q) have been calibrated in this way the DAC
outputs will not change until the chip is powered down or the
calibration circuit is re-activated in some other way.
FM Receive Signal Path
In FM mode two low speed 8-bit ADCs are used to digitise
the incoming signals before subsequent transmission to the
baseband digital signal processor as two serial 8-bit words
(FMRXI & FMRXQ). The sample rate is entirely determined by
the digital baseband processor (up-to the maximum allowed)
via the FMCLK input.
In FM mode the receive filters are assumed to track the
filters used in CDMA mode i.e. there is no separate tuning
mechanism.
SYNTHESISERS
The Synthesiser block comprises the input buffers, main
dividers, phase comparator, charge pump and lock detect
circuit for a TX and RX synthesiser. The loop filter components
and the VCOs are external to the device. A common reference
divider chain is also included together with bias and control
circuitry. All blocks apart from reference divider, bias and
control logic are duplicated exactly for RX and TX
synthesisers.
The receive intermediate frequency (RX_IF) is
programmable and the transmit intermediate frequency
(TX_IF) is fixed at 130.38MHz.
AUX ADC
The auxiliary converter section contains a single 8-bit
successive approximation analog to digital converter, with
serial output. In order to maximise the flexibility of Pluto, a 4
way analog multiplexer is provided, which enables the
converter to encode any one of four selectable channels. The
converter is intended for such applications as power supply
and temperature monitoring. When not in use, the converter is
powered down, and its outputs are held low.
4
PLUTO
TIMING INFORMATION
Parameter
Min
t1
t2
t3
t4
t5
t6
t7
t8
TXCLOCK PERIOD (CDMA TX)
TXCLOCK HIGH TIME (CDMA TX)
TXCLOCK LOW TIME (CDMA TX)
TXCLOCK PHASE Delay (CDMA TX)
TXCLOCK RISE TIME (CDMA TX)
TXCLOCK FALL TIME (CDMA TX)
TXD-TXCLOCK SETUP TIME
TXCLOCK-TXD HOLD TIME
20
3
2.78
1.39
1.39
101.6
50.8
50.8
3
3
10
20
2.78
1.39
1.39
12
12
1
50
50
50
40
100
100
2.44
0.81
1.62
12
12
1
5
20
20
50
20
50
100
152.4
12
12
Value
Typ
203.2
101.6
101.6
1.2
12
12
Max
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
µs
ns
ns
ns
µs
ns
ns
µs
µs
µs
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
CDMA TX Figure 3
CDMA TX Figure 3
CDMA TX Figure 3
CDMA TX Figure 3, FM TX Figure 4
CDMA TX Figure 3, FM TX Figure 4
CDMA TX Figure 3, FM TX Figure 4
CDMA TX Figure 3, FM TX Figure 4
CDMA TX Figure 3, FM TX Figure 4
FM TX Figure 4
FM TX Figure 4
FM TX Figure 4
Figure 5
Figure 5
Figure 5
Figure 5
Figure 5
Figure 5
Figure 5
FM RX Figure 6
FM RX Figure 6
FM RX Figure 6
FM RX Figure 6
FM RX Figure 6
FM RX Figure 6
FM RX Figure 6
FM RX Figure 6
FM RX Figure 6
General purpose ADC Figure 7
General purpose ADC Figure 7
General purpose ADC Figure 7
General purpose ADC Figure 7
General purpose ADC Figure 7
General purpose ADC Figure 7
General purpose ADC Figure 7
General purpose ADC Figure 7
General purpose ADC Figure 7
General purpose ADC Figure 7
Serial Interface Figure 8
Serial Interface Figure 8
Serial Interface Figure 8
Serial Interfsce Figure 8
Serial Interface Figure 8
Serial Interface Figure 8
Units
Conditions
t11 TXCLOCK PERIOD (FM TX)
t12 TXCLOCK HIGH TIME (FM TX)
t13 TXCLOCK LOW TIME (FM TX)
t14 CHIPx8 PERIOD
t15 CHIPx8 HIGH TIME
t16 CHIPx8LOW TIME
t17 CHIPx8 RISE TIME
t18 CHIPx8 FALL TIME
t19 RXD Hold Time After CHIPx8↓
t20 RXD DELAY After CHIPx8↓
t21 FMCLK PERIOD
t22 FMCLK HIGH TIME
t23 FMCLK LOW TIME
t24 FMCLK RISE TIME
t25 FMCLK FALL TIME
t26 RXFMSTB HIGH TIME
t27 RXFMSTB -FMCLK↓ SETUP TIME
t28 FMCLK↓
−
RXFMSTB HOLD TIME
t29 FMCLK↓
−
OUTPUT DATA DELAY
t30 ADCENA HIGH _ CONVERSION
t31 ADCENA HIGH TIME
t32 ADCENA LOW TIME
t33 ADCCLK PERIOD
t34 ADCCLK HIGH TIME
t35 ADCCLK LOW TIME
t36 ADCCLK RISE TIME
t37 ADCCLK FALL TIME
t38 ADCDATA VALID BEFORE ADCCLK↑
t39 ADC DATA HOLD TIME
t40 SCLK-SDATA setup time
t41 SCLK-SDATA hold time
t42 SCLK pulse width
t43 SLATCH-SCLK setup time
t44 SLATCH pulse width
t45 SCLK period
5
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