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and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
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SPECIAL DAMAGES, HOWEVER THEY MAY ARISE, AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES. The code
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About This Manual
®
Notes
Introduction
This user manual includes hardware and software information on the 89HPES24T3G2, a member of
IDT’s PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect
standard.
Finding Additional Information
Information not included in this manual such as mechanicals, package pin-outs, and electrical character-
istics can be found in the data sheet for this device, which is available from the IDT website
(www.idt.com)
as well as through your local IDT sales representative.
Content Summary
Chapter 1, “PES24T3G2 Device Overview,”
provides a complete introduction to the performance
capabilities of the 89HPES24T3G2. Included in this chapter is a summary of features for the device as well
as a system block diagram and pin description.
Chapter 2, “Clocking, Reset, and Initialization,”
provides a description of the two differential refer-
ence clock inputs that are used internally to generate all of the clocks required by the internal switch logic
and the SerDes.
Chapter 3, “Link Operation,”
describes the operation of the link feature including polarity inversion,
link width negotiation, and lane reversal.
Chapter 4, “General Purpose I/O,”
describes how the 8 General Purpose I/O (GPIO) pins may be indi-
vidually configured as general purpose inputs, general purpose outputs, or alternate functions.
Chapter 5, “SMBus Interfaces,”
describes the operation of the 2 SMBus interfaces on the
PES24T3G2.
Chapter 6, “Power Management,”
describes the power management capability structure located in the
configuration space of each PCI-PCI bridge in the PES24T3G2.
Chapter 7, “Hot-Plug and Hot-Swap,”
describes the behavior of the hot-plug and hot-swap features in
the PES24T3G2.
Chapter 8, “Configuration Registers,”
discusses the base addresses, PCI configuration space, and
registers associated with the PES24T3G2.
Chapter 9, “JTAG Boundary Scan,”
discusses an enhanced JTAG interface, including a system logic
TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.
Signal Nomenclature
To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms
assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or
true, independent of whether that level is represented by a high or low voltage. The term negate or negation
is used to indicate that a signal is inactive or false.
To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter-
preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,
buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.
To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on
the right. No leading zeros will be included.
PES24T3G2 User Manual
1
February 22, 2012
IDT
Notes
Throughout this manual, when describing signal transitions, the following terminology is used. Rising
edge indicates a low-to-high (0 to 1) transition. Falling edge indicates a high-to-low (1 to 0) transition. These
terms are illustrated in Figure 1.
single clock cycle
1
2
3
4
high-to-low
transition
low-to-high
transition
Figure 1 Signal Transitions
Numeric Representations
To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.
The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.
The compressed notation ABC[x..y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD.
Data Units
The following data unit terminology is used in this document.
Term
Byte
Word
Doubleword (Dword)
Quadword (Qword)
Words
1/2
1
2
4
Bytes
1
2
4
8
Bits
8
16
32
64
Table 1 Data Unit Terminology
In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double-
words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15 is always
the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit
and bit 0 is the least significant bit.
The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian
systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte
zero as the least significant (rightmost) byte of a word. See Figure 2.
PES24T3G2 User Manual
2
February 22, 2012
IDT
Notes
bit 31
bit 0
0
1
2
3
Address of Bytes within Words: Big Endian
bit 31
bit 0
3
2
1
0
Address of Bytes within Words: Little Endian
Figure 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition
Register Terminology
Software in the context of this register terminology refers to modifications made by PCIe root configura-
tion writes, writes to registers made through the slave SMBus interface, or serial EEPROM register initial-
ization. See Table 2.
Type
Hardware Initialized
Abbreviation
HWINIT
Description
Register bits are initialized by firmware or hardware mechanisms
such as pin strapping or serial EEPROM. (System firmware hard-
ware initialization is only allowed for system integrated devices.)
Bits are read-only after initialization and can only be reset (for
write-once by firmware) with reset.
Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bit to be reset to zero.
Writing to a RC location has no effect.
Software can read the register/bits with this attribute. Reading the
value will automatically cause the register/bits to be reset to zero.
Writes cause the register/bits to be modified.
The value read from a reserved register/bit is undefined. Thus,
software must deal correctly with fields that are reserved. On
reads, software must use appropriate masks to extract the defined
bits and not rely on reserved bits being any particular value. On
writes, software must ensure that the values of reserved bit posi-
tions are preserved. That is, the values of reserved bit positions
must first be read, merged with the new values for other bit posi-
tions and then written back.
Software can only read registers/bits with this attribute. Contents
are hardwired to a constant value or are status bits that may be
set and cleared by hardware. Writing to a RO location has no
effect.
Software can both read and write bits with this attribute.
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