MT58V512V36FT-10IT datasheet, PDF

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MT58V512V36FT-10IT: DescriptionSRAM; Categorystorage storage; File Size538KB，34 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/

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MT58V512V36FT-10IT Overview

SRAM

MT58V512V36FT-10IT Parametric

Parameter Name	Attribute value
Maker	Micron Technology
package instruction	,
Reach Compliance Code	unknow

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18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH SYNCBURST SRAM

18Mb

SRAM

Features

SYNCBURST

™

MT58L1MY18F, MT58V1MV18F,

MT58L512Y32F, MT58V512V32F,

MT58L512Y36F, MT58V512V36F

3.3V V

, 3.3V or 2.5V I/O; 2.5V V

, 2.5V I/O

• Fast clock and OE# access times

• Single 3.3V ±5 percent or 2.5V ±5 percent power supply

• Separate 3.3V±5 percent or 2.5V ±5 percent isolated

output buffer supply (V

• SNOOZE MODE for reduced-power standby

• Common data inputs and data outputs

• Individual byte write control and global write

• Three chip enables for simple depth expansion and

address pipelining

• Clock-controlled and registered addresses, data

I/Os, and control signals

• Internally self-timed write cycle

• Burst control (interleaved or linear burst)

• Low capacitive bus loading

Figure 1: 100-Pin TQFP

JEDEC-Standard MS-026 BHA (LQFP)

Figure 2: 165-Ball FBGA

JEDEC-Standard MO-216 (Var. CAB-1)

Options

• Timing (Access/Cycle/MHz)

6.8ns/7.5ns/133 MHz

7.5ns/8.8ns/113 MHz

8.5ns/10ns/100 MHz

10ns/15ns/66 MHz

• Configurations

3.3V V

, 3.3V or 2.5V I/O

1 Meg x 18

512K x 32

512K x 36

2.5V V

, 2.5V I/O

1 Meg x 18

512K x 32

512K x 36

• Packages

100-pin TQFP

165-ball, 13mm x 15mm FBGA

• Operating Temperature Range

Commercial (0ºC

+70ºC)

Industrial (-40ºC

+85ºC)

NOTE:

TQFP

Marking

-6.8

-7.5

-8.5

-10

MT58L1MY18F

MT58L512Y32F

MT58L512Y36F

MT58V1MV18F

MT58V512V32F

MT58V512V36F

None

Part Number Example:

MT58L512Y36FT-10

General Description

The Micron

SyncBurst™ SRAM family employs

high-speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

Micron’s 18Mb SyncBurst SRAMs integrate a 1 Meg x

18, 512K x 32, or 512K x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst

counter. All synchronous inputs pass through registers

controlled by a positive-edge-triggered single-clock

input (CLK). The synchronous inputs include all

addresses, all data inputs, active LOW chip enable

(CE#), two additional chip enables for easy depth

expansion (CE2#, CE2), burst control inputs (ADSC#,

ADSP#, ADV#), byte write enables (BWx#), and global

write (GW#).

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

2. Contact factory for availability of Industrial Temperature

devices.

18Mb: 1 Meg x 18, 512K x 32/36, Flow-Through SyncBurst SRAM

MT58L1MY18F_16_D.fm – Rev. D, Pub. 2/03

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH SYNCBURST SRAM

Table 1:

SYMBOL

ADSC#

TQFP Pin Descriptions

TYPE

Input

DESCRIPTION

Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst,

causing a new external address to be registered. A READ or WRITE is performed using the

new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when

CE# is HIGH.

Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst,

causing a new external address to be registered. A READ is performed using the new address,

independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#.

ADSP# is ignored if CE# is HIGH. Power-down state is entered if CE2 is LOW or CE2# is HIGH.

Synchronous Address Advance: This active LOW input is used to advance the internal burst

counter, controlling burst access after the external address is loaded. A HIGH on this pin

effectively causes wait states to be generated (no address advance). To ensure use of correct

address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an

ADSP# cycle is initiated.

Synchronous Byte Write: These active LOW inputs allow individual bytes to be written when a

WRITE cycle is active and must meet the setup and hold times around the rising edge of CLK.

BWs need to be asserted on the same cycle as the address. To enable the BW’s functionality,

the byte write enable (BWE#) input must be asserted LOW. BWa# controls DQa pins; BWb#

controls DQb pins; BWc# controls DQc pins; and BWd# controls DQa pins.

Byte Write Enable: This active LOW input permits byte write operations and must meet the

setup and hold times around the rising edge of CLK.

Synchronous Chip Enable: This active LOW input is used to enable the device and conditions

the internal use of ADSP#. CE# is sampled only when a new external address is loaded.

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled

only when a new external address is loaded.

Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled

only when a new external address is loaded.

Clock: CLK registers address, data, chip enable, byte write enables, and burst control inputs

on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s

rising edge.

Global Write: This active LOW input allows a full 18-, 32-, or 36-bit WRITE to occur

independent of the BWE# and BWx# lines and must meet the setup and hold times around

the rising edge of CLK.

Mode: This input selects the burst sequence. A low on this pin selects “linear burst.” NC or

HIGH on this pin selects “interleaved burst.” Do not alter input state while device is

operating. LBO# is the JEDEC-standard term for MODE.

Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G# is

the JEDEC-standard term for OE#.

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold

times around the rising edge of CLK.

Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power

standby mode in which all data in the memory array is retained. When ZZ is active, all other

inputs are ignored. This pin has an internal pull-down and can be left unconnected.

SRAM Data I/Os: For the x18 version, byte “a” is associated with DQa pins; byte “b” is

associated with DQb pins. For the x32 and x36 versions, byte “a” is associated with DQa pins;

byte “b” is associated with DQb pins; byte “c” is associated with DQc pins; byte “d” is

associated with DQd pins. Input data must meet setup and hold times around the rising edge

of CLK.

ADSP#

Input

ADV#

Input

BWa#

BWb#

BWc#

BWd#

BWE#

CE#

CE2#

CE2

CLK

Input

GW#

Input

MODE

(LBO#)

OE#

(G#)

SA0

SA1

Input

DQa

DQb

DQc

DQd

Input/

Output

18Mb: 1 Meg x 18, 512K x 32/36, Flow-Through SyncBurst SRAM

MT58L1MY18F_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

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