MC74HCT595A
8-Bit Serial-Input/Serial or
Parallel-Output Shift
Register with Latched
3-State Outputs and LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT595A consists of an 8−bit shift register and an 8−bit
D−type latch with three−state parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register also
provides parallel data to the 8−bit latch. The shift register and latch
have independent clock inputs. This device also has an asynchronous
reset for the shift register.
The HCT595A directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs. The device inputs are compatible with
standard CMOS or LSTTL outputs.
Features
SOIC−16
D SUFFIX
CASE 751B
1
16
TSSOP−16
DT SUFFIX
CASE 948F
1
A
WL, L
YY, Y
WW, W
G,
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
HCT
595A
ALYWG
G
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MARKING
DIAGRAMS
16
16
1
HCT595AG
AWLYWW
16
1
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC
Standard No. 7A
•
Chip Complexity: 328 FETs or 82 Equivalent Gates
•
Improvements over HC595 / HCT595
−
Improved Propagation Delays
−
50% Lower Quiescent Power
−
Improved Input Noise and Latchup Immunity
•
Pb−Free Packages are Available*
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
1
Publication Order Number:
MC74HCT595A/D
©
Semiconductor Components Industries, LLC, 2011
March, 2011
−
Rev. 1
MC74HCT595A
LOGIC DIAGRAM
SERIAL
DATA
INPUT
A
14
15
1
2
3
SHIFT
REGISTER
4
LATCH
5
6
7
SHIFT 11
CLOCK
10
RESET
LATCH 12
CLOCK
OUTPUT 13
ENABLE
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
PARALLEL
DATA
OUTPUTS
PIN ASSIGNMENT
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q
A
A
OUTPUT ENABLE
LATCH CLOCK
SHIFT CLOCK
RESET
SQ
H
9
SQ
H
SERIAL
DATA
OUTPUT
V
CC
= PIN 16
GND = PIN 8
ORDERING INFORMATION
Device
MC74HCT595ADG
MC74HCT595ADR2G
MC74HCT595ADTG
MC74HCT595ADTR2G
Package
SOIC−16
(Pb−Free)
SOIC−16
(Pb−Free)
TSSOP−16*
TSSOP−16*
(Pb−Free)
Shipping
†
48 Units / Rail
2500 Tape & Reel
96 Units / Rail
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HCT595A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol
V
CC
V
in
I
in
I
out
I
CC
P
D
T
stg
T
L
V
out
Parameter
Value
Unit
V
V
V
mA
mA
mA
mW
_C
_C
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
– 0.5 to V
CC
+ 0.5
±
20
±
35
±
75
500
450
– 65 to + 150
260
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
SOIC Package†
TSSOP Package†
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package:
−
6.1 mW/_C from 65_ to 125_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
Input Rise/Fall Time (Figure 1)
Min
4.5
0
– 55
0
Max
5.5
V
CC
+ 125
500
Unit
V
V
_C
ns
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3
MC74HCT595A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage
Maximum Low−Level Input
Voltage
Minimum High−Level Output
Voltage, Q
A
−
Q
H
Test Conditions
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
V
OL
Maximum Low−Level Output
Voltage, Q
A
−
Q
H
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
V
OH
Minimum High−Level Output
Voltage, SQ
H
Maximum Low−Level Output
Voltage, SQ
H
V
in
= V
IH
or V
IL
II
out
I
v
20
mA
V
in
= V
IH
or V
IL
V
OL
V
in
= V
IH
or V
IL
II
out
I
v
20
mA
V
in
= V
IH
or V
IL
I
in
I
OZ
Maximum Input Leakage
Current
Maximum Three−State
Leakage
Current, Q
A
−
Q
H
Maximum Quiescent Supply
Current (per Package)
Additional Quiescent Supply
Current
V
in
= V
CC
or GND
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
l
out
= 0
mA
V
in
= 2.4V, Any One Input
V
in
= V
CC
or GND, Other Inputs
I
out
= 0mA
II
out
I
v
4.0 mA
II
out
I
v
4.0 mA
|I
out
|
v
6.0 mA
|I
out
|
v
6.0 mA
V
CC
V
4.5
to
5.5
4.5
to
5.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
5.5
5.5
Guaranteed Limit
– 55 to 25_C
2.0
v
85_C
2.0
v
125_C
2.0
Unit
V
V
IL
0.8
0.8
0.8
V
V
OH
4.4
3.98
0.1
0.26
4.4
3.98
0.1
0.26
±
0.1
±
0.5
4.4
3.84
0.1
0.33
4.4
3.84
0.1
0.33
±
1.0
±
5.0
4.4
3.7
0.1
0.4
4.4
3.7
0.1
0.4
±
1.0
±
10
V
V
V
V
mA
mA
I
CC
5.5
4.0
40
160
mA
DI
CC
≥
−55°C
5.5
2.9
25 to 125°C
2.4
mA
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4
MC74HCT595A
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbol
f
max
t
PLH
,
t
PHL
t
PHL
t
PLH
,
t
PHL
t
PLZ
,
t
PHZ
t
PZL
,
t
PZH
t
TLH
,
t
THL
t
TLH
,
t
THL
C
in
C
out
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
Maximum Propagation Delay, Shift Clock to SQ
H
(Figures 1 and 7)
Maximum Propagation Delay, Reset to SQ
H
(Figures 2 and 7)
Maximum Propagation Delay, Latch Clock to Q
A
−
Q
H
(Figures 3 and 7)
Maximum Propagation Delay, Output Enable to Q
A
−
Q
H
(Figures 4 and 8)
Maximum Propagation Delay, Output Enable to Q
A
−
Q
H
(Figures 4 and 8)
Maximum Output Transition Time, Q
A
−
Q
H
(Figures 3 and 7)
Maximum Output Transition Time, SQ
H
(Figures 1 and 7)
Maximum Input Capacitance
Maximum Three−State Output Capacitance (Output in
High−Impedance State), Q
A
−
Q
H
V
CC
V
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
—
—
Guaranteed Limit
– 55 to 25_C
30
28
29
28
30
27
12
15
10
15
v
85_C
24
35
36
35
38
34
15
19
10
15
v
125_C
20
42
44
42
45
41
18
22
10
15
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
pF
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Package)*
2
f
300
+ I
CC
V
CC
.
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
TIMING REQUIREMENTS
(Input t
r
= t
f
= 6.0 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Î
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Î
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Î Î
Î
ÎÎÎ Î Î
Î
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Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎ Î
Î Î Î
Î
Î
Î Î Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î
Î Î
Î
Symbol
t
su
t
su
t
h
Parameter
V
CC
V
Guaranteed Limit
v
85_C
13
19
25_C to –55_C
10
15
v
125_C
15
22
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
4.5 to
5.5
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
5.0
10
12
10
10
5.0
13
15
13
13
5.0
15
18
15
15
t
rec
t
w
t
w
t
w
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
Minimum Pulse Width, Reset
(Figure 2)
Minimum Pulse Width, Shift Clock
(Figure 1)
Minimum Pulse Width, Latch Clock
(Figure 6)
t
r
, t
f
Maximum Input Rise and Fall Times
(Figure 1)
500
500
500
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